Commit 333fe325 authored by Thong Thai's avatar Thong Thai Committed by Alex Deucher
Browse files

drm/amd/amdgpu/vcn_v2_0: Mark RB commands as KMD commands 



Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This
bit was previously set by the RBC HW on older firmware. Newer firmware
uses a SW RBC and this bit has to be set by the driver.

Signed-off-by: default avatarThong Thai <thong.thai@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d3b9f39d

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+1 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 
#define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)

#define AMDGPU_VCN_HARVEST_VCN1 (1 << 1)



#define VCN_DEC_KMD_CMD 		0x80000000

#define VCN_DEC_CMD_FENCE		0x00000000

#define VCN_DEC_CMD_TRAP		0x00000001

#define VCN_DEC_CMD_WRITE_REG		0x00000004

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

+6 −6
Original line number Diff line number Diff line
@@ -1494,7 +1494,7 @@ void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) 
	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));

	amdgpu_ring_write(ring, 0);

	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));

	amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);

	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));

}



/**
@@ -1509,7 +1509,7 @@ void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) 
	struct amdgpu_device *adev = ring->adev;



	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));

	amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);

	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));

}



/**
@@ -1556,7 +1556,7 @@ void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 
	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);



	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));

	amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);

	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));



	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));

	amdgpu_ring_write(ring, 0);
@@ -1566,7 +1566,7 @@ void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 


	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));



	amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);

	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));

}



/**
@@ -1612,7 +1612,7 @@ void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 


	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));



	amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);

	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));

}



void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
@@ -1643,7 +1643,7 @@ void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 


	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));



	amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);

	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));

}



/**

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