drm/i915/gen12: Fix HDC pipeline flush (32d7171e) · Commits · 戴 / test

drivers/gpu/drm/i915/gt/intel_engine.h

+28 −6

Original line number	Diff line number	Diff line
		@@ -241,19 +241,29 @@ void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
		void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine,
		struct drm_printer *p);

		static inline u32 gen8_emit_pipe_control(u32 batch, u32 flags, u32 offset)
		static inline u32 __gen8_emit_pipe_control(u32 batch, u32 flags0, u32 flags1, u32 offset)
		{
		memset(batch, 0, 6 * sizeof(u32));

		batch[0] = GFX_OP_PIPE_CONTROL(6);
		batch[1] = flags;
		batch[0] = GFX_OP_PIPE_CONTROL(6) \| flags0;
		batch[1] = flags1;
		batch[2] = offset;

		return batch + 6;
		}

		static inline u32 gen8_emit_pipe_control(u32 batch, u32 flags, u32 offset)
		{
		return __gen8_emit_pipe_control(batch, 0, flags, offset);
		}

		static inline u32 gen12_emit_pipe_control(u32 batch, u32 flags0, u32 flags1, u32 offset)
		{
		return __gen8_emit_pipe_control(batch, flags0, flags1, offset);
		}

		static inline u32 *
		gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
		__gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)
		{
		/* We're using qword write, offset should be aligned to 8 bytes. */
		GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
		@@ -262,8 +272,8 @@ gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
		* need a prior CS_STALL, which is emitted by the flush
		* following the batch.
		*/
		*cs++ = GFX_OP_PIPE_CONTROL(6);
		*cs++ = flags \| PIPE_CONTROL_QW_WRITE \| PIPE_CONTROL_GLOBAL_GTT_IVB;
		*cs++ = GFX_OP_PIPE_CONTROL(6) \| flags0;
		*cs++ = flags1 \| PIPE_CONTROL_QW_WRITE \| PIPE_CONTROL_GLOBAL_GTT_IVB;
		*cs++ = gtt_offset;
		*cs++ = 0;
		*cs++ = value;
		@@ -273,6 +283,18 @@ gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
		return cs;
		}

		static inline u32*
		gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
		{
		return __gen8_emit_ggtt_write_rcs(cs, value, gtt_offset, 0, flags);
		}

		static inline u32*
		gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)
		{
		return __gen8_emit_ggtt_write_rcs(cs, value, gtt_offset, flags0, flags1);
		}

		static inline u32 *
		gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
		{

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -237,7 +237,7 @@
		#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on ILK */
		#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
		#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
		#define PIPE_CONTROL_HDC_PIPELINE_FLUSH REG_BIT(9) /* gen12 */
		#define PIPE_CONTROL0_HDC_PIPELINE_FLUSH REG_BIT(9) /* gen12 */
		#define PIPE_CONTROL_NOTIFY (1<<8)
		#define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
		#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)

drivers/gpu/drm/i915/gt/intel_lrc.c

+15 −14

Original line number	Diff line number	Diff line
		@@ -4553,7 +4553,6 @@ static int gen12_emit_flush_render(struct i915_request *request,
		flags \|= PIPE_CONTROL_DEPTH_STALL;
		flags \|= PIPE_CONTROL_DC_FLUSH_ENABLE;
		flags \|= PIPE_CONTROL_FLUSH_ENABLE;
		flags \|= PIPE_CONTROL_HDC_PIPELINE_FLUSH;

		flags \|= PIPE_CONTROL_STORE_DATA_INDEX;
		flags \|= PIPE_CONTROL_QW_WRITE;
		@@ -4564,7 +4563,9 @@ static int gen12_emit_flush_render(struct i915_request *request,
		if (IS_ERR(cs))
		return PTR_ERR(cs);

		cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
		cs = gen12_emit_pipe_control(cs,
		PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
		flags, LRC_PPHWSP_SCRATCH_ADDR);
		intel_ring_advance(request, cs);
		}

		@@ -4751,9 +4752,10 @@ static u32 gen12_emit_fini_breadcrumb(struct i915_request rq, u32 *cs)
		static u32 *
		gen12_emit_fini_breadcrumb_rcs(struct i915_request request, u32 cs)
		{
		cs = gen8_emit_ggtt_write_rcs(cs,
		cs = gen12_emit_ggtt_write_rcs(cs,
		request->fence.seqno,
		i915_request_active_timeline(request)->hwsp_offset,
		PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
		PIPE_CONTROL_CS_STALL \|
		PIPE_CONTROL_TILE_CACHE_FLUSH \|
		PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH \|
		@@ -4761,8 +4763,7 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request request, u32 cs)
		/* Wa_1409600907:tgl */
		PIPE_CONTROL_DEPTH_STALL \|
		PIPE_CONTROL_DC_FLUSH_ENABLE \|
		PIPE_CONTROL_FLUSH_ENABLE \|
		PIPE_CONTROL_HDC_PIPELINE_FLUSH);
		PIPE_CONTROL_FLUSH_ENABLE);

		return gen12_emit_fini_breadcrumb_tail(request, cs);
		}

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