Commit 31d0271d authored by Yintian Tao's avatar Yintian Tao Committed by Alex Deucher
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drm/amdgpu: miss PRT case when bo update



Originally, only the PTE valid is taken in consider.
The PRT case is missied when bo update which raise problem.
We need add condition for PRT case.

v2: add PRT condition for amdgpu_vm_bo_update_mapping, too
v3: fix one typo error

Signed-off-by: default avatarYintian Tao <yttao@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7287a675
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+3 −3
Original line number Diff line number Diff line
@@ -1446,7 +1446,7 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
		uint64_t incr, entry_end, pe_start;
		struct amdgpu_bo *pt;

		if (flags & AMDGPU_PTE_VALID) {
		if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
			/* make sure that the page tables covering the
			 * address range are actually allocated
			 */
@@ -1603,7 +1603,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
		goto error_unlock;
	}

	if (flags & AMDGPU_PTE_VALID) {
	if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
		struct amdgpu_bo *root = vm->root.base.bo;

		if (!dma_fence_is_signaled(vm->last_direct))
@@ -1715,7 +1715,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
					AMDGPU_GPU_PAGES_IN_CPU_PAGE;
			}

		} else if (flags & AMDGPU_PTE_VALID) {
		} else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
			addr += bo_adev->vm_manager.vram_base_offset;
			addr += pfn << PAGE_SHIFT;
		}