Commit 7287a675 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
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drm/amd/display: add on demand pipe merge logic for dcn2+ 



Adds logic that will determine if pipes need merging during validation.

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarChris Park <Chris.Park@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2277f01d

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+5 −2
Original line number Diff line number Diff line
@@ -893,6 +893,7 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx) 
	int vpc_div = (data->format == PIXEL_FORMAT_420BPP8

			|| data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;

	bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;

	int odm_idx = 0;



	/*

	 * Need to calculate the scan direction for viewport to make adjustments
@@ -924,11 +925,13 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx) 
					* stream->dst.width / stream->src.width -

					src.x * plane_state->dst_rect.width / src.width

					* stream->dst.width / stream->src.width);

	/*modified recout_skip_h calculation due to odm having no recout offset caused by split*/

	/*modified recout_skip_h calculation due to odm having no recout offset*/

	while (odm_pipe) {

		recout_skip_h += odm_pipe->plane_res.scl_data.recout.width + odm_pipe->plane_res.scl_data.recout.x;

		odm_idx++;

		odm_pipe = odm_pipe->prev_odm_pipe;

	}

	if (odm_idx)

		recout_skip_h += odm_idx * data->recout.width;



	recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)

					* stream->dst.height / stream->src.height -

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+46 −10
Original line number Diff line number Diff line
@@ -1671,7 +1671,7 @@ static void acquire_dsc(struct resource_context *res_ctx, 
		}

}



static void release_dsc(struct resource_context *res_ctx,

void dcn20_release_dsc(struct resource_context *res_ctx,

			const struct resource_pool *pool,

			struct display_stream_compressor **dsc)

{
@@ -1731,7 +1731,7 @@ static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, 
			pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];



			if (pipe_ctx->stream_res.dsc)

				release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);

				dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);

		}

	}
@@ -2502,7 +2502,7 @@ struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, 
	return secondary_pipe;

}



void dcn20_merge_pipes_for_validate(

static void dcn20_merge_pipes_for_validate(

		struct dc *dc,

		struct dc_state *context)

{
@@ -2527,7 +2527,7 @@ void dcn20_merge_pipes_for_validate( 
			odm_pipe->prev_odm_pipe = NULL;

			odm_pipe->next_odm_pipe = NULL;

			if (odm_pipe->stream_res.dsc)

				release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);

				dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);

			/* Clear plane_res and stream_res */

			memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));

			memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
@@ -2565,7 +2565,8 @@ int dcn20_validate_apply_pipe_split_flags( 
		struct dc *dc,

		struct dc_state *context,

		int vlevel,

		bool *split)

		bool *split,

		bool *merge)

{

	int i, pipe_idx, vlevel_split;

	int plane_count = 0;
@@ -2609,11 +2610,12 @@ int dcn20_validate_apply_pipe_split_flags( 
	/* Split loop sets which pipe should be split based on dml outputs and dc flags */

	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

		int pipe_plane = context->bw_ctx.dml.vba.pipe_plane[pipe_idx];



		if (!context->res_ctx.pipe_ctx[i].stream)

			continue;



		if (force_split || context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] > 1)

		if (force_split || context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_plane] > 1)

			split[i] = true;

		if ((pipe->stream->view_format ==

				VIEW_3D_FORMAT_SIDE_BY_SIDE ||
@@ -2626,10 +2628,44 @@ int dcn20_validate_apply_pipe_split_flags( 
			split[i] = true;

		if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {

			split[i] = true;

			context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = dm_odm_combine_mode_2to1;

			context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;

		}

		context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_plane] =

			context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_plane];



		if (pipe->prev_odm_pipe && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_plane] != dm_odm_combine_mode_disabled) {

			/*Already split odm pipe tree, don't try to split again*/

			split[i] = false;

			split[pipe->prev_odm_pipe->pipe_idx] = false;

		} else if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state

				&& context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) {

			/*Already split mpc tree, don't try to split again, assumes only 2x mpc combine*/

			split[i] = false;

			split[pipe->top_pipe->pipe_idx] = false;

		} else if (pipe->prev_odm_pipe || (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)) {

			if (split[i] == false) {

				/*Exiting mpc/odm combine*/

				merge[i] = true;

				if (pipe->prev_odm_pipe) {

					ASSERT(0); /*should not actually happen yet*/

					merge[pipe->prev_odm_pipe->pipe_idx] = true;

				} else

					merge[pipe->top_pipe->pipe_idx] = true;

			} else {

				/*Transition from mpc combine to odm combine or vice versa*/

				ASSERT(0); /*should not actually happen yet*/

				split[i] = true;

				merge[i] = true;

				if (pipe->prev_odm_pipe) {

					split[pipe->prev_odm_pipe->pipe_idx] = true;

					merge[pipe->prev_odm_pipe->pipe_idx] = true;

				} else {

					split[pipe->top_pipe->pipe_idx] = true;

					merge[pipe->top_pipe->pipe_idx] = true;

				}

		context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] =

			context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];

			}

		}



		/* Adjust dppclk when split is forced, do not bother with dispclk */

		if (split[i] && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)

			context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
@@ -2671,7 +2707,7 @@ bool dcn20_fast_validate_bw( 
	if (vlevel > context->bw_ctx.dml.soc.num_states)

		goto validate_fail;



	vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split);

	vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);



	/*initialize pipe_just_split_from to invalid idx*/

	for (i = 0; i < MAX_PIPES; i++)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h

+5 −4
Original line number Diff line number Diff line
@@ -119,14 +119,15 @@ void dcn20_set_mcif_arb_params( 
		display_e2e_pipe_params_st *pipes,

		int pipe_cnt);

bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate);

void dcn20_merge_pipes_for_validate(

		struct dc *dc,

		struct dc_state *context);

int dcn20_validate_apply_pipe_split_flags(

		struct dc *dc,

		struct dc_state *context,

		int vlevel,

		bool *split);

		bool *split,

		bool *merge);

void dcn20_release_dsc(struct resource_context *res_ctx,

			const struct resource_pool *pool,

			struct display_stream_compressor **dsc);

bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx);

void dcn20_split_stream_for_mpc(

		struct resource_context *res_ctx,

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