iommu/io-pgtable-arm: Support non-coherent stage-2 page tables (30d2acb6) · Commits · 戴 / test

Commit ("iommu/io-pgtable: Support non-coherent page tables") added support for non-coherent page-table walks to the Arm IOMMU page-table backends. Unfortunately, it left the stage-2 allocator unchanged, so let's hook that up in the same way. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Robin Murphy <robin.murphy@arm.com> Signed-off-by:

Will Deacon <will@kernel.org>

drivers/iommu/io-pgtable-arm.c

+10 −4

Original line number	Diff line number	Diff line
		@@ -910,10 +910,16 @@ arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg cfg, void cookie)
		}

		/* VTCR */
		reg = ARM_64_LPAE_S2_TCR_RES1 \|
		(ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) \|
		reg = ARM_64_LPAE_S2_TCR_RES1;
		if (cfg->coherent_walk) {
		reg \|= (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) \|
		(ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) \|
		(ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);
		} else {
		reg \|= (ARM_LPAE_TCR_SH_OS << ARM_LPAE_TCR_SH0_SHIFT) \|
		(ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_IRGN0_SHIFT) \|
		(ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_ORGN0_SHIFT);
		}

		sl = data->start_level;

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