Commit d1e5f26f authored by Robin Murphy's avatar Robin Murphy Committed by Will Deacon
Browse files

iommu/io-pgtable-arm: Rationalise TTBRn handling 



TTBR1 values have so far been redundant since no users implement any
support for split address spaces. Crucially, though, one of the main
reasons for wanting to do so is to be able to manage each half entirely
independently, e.g. context-switching one set of mappings without
disturbing the other. Thus it seems unlikely that tying two tables
together in a single io_pgtable_cfg would ever be particularly desirable
or useful.

Streamline the configs to just a single conceptual TTBR value
representing the allocated table. This paves the way for future users to
support split address spaces by simply allocating a table and dealing
with the detailed TTBRn logistics themselves.

Tested-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: default avatarRobin Murphy <robin.murphy@arm.com>
[will: Drop change to ttbr value]
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent cd037ff2

drivers/iommu/arm-smmu-v3.c

+1 −1
Original line number Diff line number Diff line
@@ -2166,7 +2166,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, 
	}



	cfg->cd.asid	= (u16)asid;

	cfg->cd.ttbr	= pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];

	cfg->cd.ttbr	= pgtbl_cfg->arm_lpae_s1_cfg.ttbr;

	cfg->cd.tcr	= pgtbl_cfg->arm_lpae_s1_cfg.tcr;

	cfg->cd.mair	= pgtbl_cfg->arm_lpae_s1_cfg.mair;

	return 0;

drivers/iommu/arm-smmu.c

+4 −5
Original line number Diff line number Diff line
@@ -553,13 +553,12 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, 
	/* TTBRs */

	if (stage1) {

		if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {

			cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr[0];

			cb->ttbr[1] = pgtbl_cfg->arm_v7s_cfg.ttbr[1];

			cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr;

			cb->ttbr[1] = 0;

		} else {

			cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];

			cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;

			cb->ttbr[0] |= FIELD_PREP(TTBRn_ASID, cfg->asid);

			cb->ttbr[1] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];

			cb->ttbr[1] |= FIELD_PREP(TTBRn_ASID, cfg->asid);

			cb->ttbr[1] = FIELD_PREP(TTBRn_ASID, cfg->asid);

		}

	} else {

		cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;

drivers/iommu/io-pgtable-arm-v7s.c

+8 −9
Original line number Diff line number Diff line
@@ -822,15 +822,14 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, 
	/* Ensure the empty pgd is visible before any actual TTBR write */

	wmb();



	/* TTBRs */

	cfg->arm_v7s_cfg.ttbr[0] = virt_to_phys(data->pgd) |

	/* TTBR */

	cfg->arm_v7s_cfg.ttbr = virt_to_phys(data->pgd) |

				ARM_V7S_TTBR_S | ARM_V7S_TTBR_NOS |

				(cfg->coherent_walk ?

				(ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |

				 ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) :

				(ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) |

				 ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC)));

	cfg->arm_v7s_cfg.ttbr[1] = 0;

	return &data->iop;



out_free_data:

drivers/iommu/io-pgtable-arm.c

+2 −3
Original line number Diff line number Diff line
@@ -872,9 +872,8 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) 
	/* Ensure the empty pgd is visible before any actual TTBR write */

	wmb();



	/* TTBRs */

	cfg->arm_lpae_s1_cfg.ttbr[0] = virt_to_phys(data->pgd);

	cfg->arm_lpae_s1_cfg.ttbr[1] = 0;

	/* TTBR */

	cfg->arm_lpae_s1_cfg.ttbr = virt_to_phys(data->pgd);

	return &data->iop;



out_free_data:

drivers/iommu/ipmmu-vmsa.c

+1 −1
Original line number Diff line number Diff line
@@ -374,7 +374,7 @@ static void ipmmu_domain_setup_context(struct ipmmu_vmsa_domain *domain) 
	u32 tmp;



	/* TTBR0 */

	ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0];

	ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr;

	ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr);

	ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32);

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