Commit 2dc4aa52 authored by James Zhu's avatar James Zhu Committed by Alex Deucher
Browse files

drm/amdgpu/vcn:fix dpg pause mode hang issue 



Use mmUVD_SCRATCH2 tracking decode write point.
It will help avoid dpg pause mode hang issue.

Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Acked-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9332ddc9

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

+2 −2
Original line number Diff line number Diff line
@@ -263,7 +263,7 @@ static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev, 


				ring = &adev->vcn.ring_dec;

				WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,

					     lower_32_bits(ring->wptr) | 0x80000000);

						   RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2));

				SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

						   UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,

						   UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
@@ -320,7 +320,7 @@ static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev, 


				ring = &adev->vcn.ring_dec;

				WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,

					     lower_32_bits(ring->wptr) | 0x80000000);

						   RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2));

				SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

						   UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,

						   UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

+8 −0
Original line number Diff line number Diff line
@@ -873,6 +873,8 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) 
	/* Initialize the ring buffer's read and write pointers */

	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);



	WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);



	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,

			lower_32_bits(ring->wptr));
@@ -1049,6 +1051,8 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) 
	/* Initialize the ring buffer's read and write pointers */

	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);



	WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);



	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,

								lower_32_bits(ring->wptr));
@@ -1215,6 +1219,10 @@ static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 
{

	struct amdgpu_device *adev = ring->adev;



	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)

		WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,

			lower_32_bits(ring->wptr) | 0x80000000);



	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

}

CRA Git | Maintained and supported by SUSTech CRA and CCSE