Commit 2d0720f5 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-fixes-2019-11-14' of... 

Merge tag 'drm-intel-next-fixes-2019-11-14' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

- PMU "Frequency" is reported as accumulated cycles
- Avoid OOPS in dumb_create IOCTL when no CRTCs
- Mitigation for userptr put_pages deadlock with trylock_page
- Fix to avoid freeing heartbeat request too early
- Fix LRC coherency issue
- Fix Bugzilla #112212: Avoid screen corruption on MST
- Error path fix to unlock context on failed context VM SETPARAM
- Always consider holding preemption a privileged op in perf/OA
- Preload LUTs if the hw isn't currently using them to avoid color flash on VLV/CHV
- Protect context while grabbing its name for the request
- Don't resize aliasing ppGTT size
- Smaller fixes picked by tooling

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191114085213.GA6440@jlahtine-desk.ger.corp.intel.com
parents dfce9025 789c4aea

drivers/gpu/drm/i915/display/intel_atomic.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -200,6 +200,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) 
	crtc_state->update_wm_pre = false;

	crtc_state->update_wm_pre = false;

	crtc_state->update_wm_post = false;

	crtc_state->update_wm_post = false;

	crtc_state->fifo_changed = false;

	crtc_state->fifo_changed = false;

	crtc_state->preload_luts = false;

	crtc_state->wm.need_postvbl_update = false;

	crtc_state->wm.need_postvbl_update = false;

	crtc_state->fb_bits = 0;

	crtc_state->fb_bits = 0;

	crtc_state->update_planes = 0;

	crtc_state->update_planes = 0;

drivers/gpu/drm/i915/display/intel_color.c

+61 −0
Original line number Original line Diff line number Diff line
@@ -1022,6 +1022,55 @@ void intel_color_commit(const struct intel_crtc_state *crtc_state) 
	dev_priv->display.color_commit(crtc_state);

	dev_priv->display.color_commit(crtc_state);

}

}





static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);

	struct intel_atomic_state *state =

		to_intel_atomic_state(new_crtc_state->base.state);

	const struct intel_crtc_state *old_crtc_state =

		intel_atomic_get_old_crtc_state(state, crtc);



	return !old_crtc_state->base.gamma_lut &&

		!old_crtc_state->base.degamma_lut;

}



static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);

	struct intel_atomic_state *state =

		to_intel_atomic_state(new_crtc_state->base.state);

	const struct intel_crtc_state *old_crtc_state =

		intel_atomic_get_old_crtc_state(state, crtc);



	/*

	 * CGM_PIPE_MODE is itself single buffered. We'd have to

	 * somehow split it out from chv_load_luts() if we wanted

	 * the ability to preload the CGM LUTs/CSC without tearing.

	 */

	if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode)

		return false;



	return !old_crtc_state->base.gamma_lut;

}



static bool glk_can_preload_luts(const struct intel_crtc_state *new_crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);

	struct intel_atomic_state *state =

		to_intel_atomic_state(new_crtc_state->base.state);

	const struct intel_crtc_state *old_crtc_state =

		intel_atomic_get_old_crtc_state(state, crtc);



	/*

	 * The hardware degamma is active whenever the pipe

	 * CSC is active. Thus even if the old state has no

	 * software degamma we need to avoid clobbering the

	 * linear hardware degamma mid scanout.

	 */

	return !old_crtc_state->csc_enable &&

		!old_crtc_state->base.gamma_lut;

}



int intel_color_check(struct intel_crtc_state *crtc_state)

int intel_color_check(struct intel_crtc_state *crtc_state)

{

{

	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);

	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
@@ -1165,6 +1214,8 @@ static int i9xx_color_check(struct intel_crtc_state *crtc_state) 
	if (ret)

	if (ret)

		return ret;

		return ret;





	crtc_state->preload_luts = intel_can_preload_luts(crtc_state);



	return 0;

	return 0;

}

}
@@ -1217,6 +1268,8 @@ static int chv_color_check(struct intel_crtc_state *crtc_state) 
	if (ret)

	if (ret)

		return ret;

		return ret;





	crtc_state->preload_luts = chv_can_preload_luts(crtc_state);



	return 0;

	return 0;

}

}
@@ -1271,6 +1324,8 @@ static int ilk_color_check(struct intel_crtc_state *crtc_state) 
	if (ret)

	if (ret)

		return ret;

		return ret;





	crtc_state->preload_luts = intel_can_preload_luts(crtc_state);



	return 0;

	return 0;

}

}
@@ -1328,6 +1383,8 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state) 
	if (ret)

	if (ret)

		return ret;

		return ret;





	crtc_state->preload_luts = intel_can_preload_luts(crtc_state);



	return 0;

	return 0;

}

}
@@ -1366,6 +1423,8 @@ static int glk_color_check(struct intel_crtc_state *crtc_state) 
	if (ret)

	if (ret)

		return ret;

		return ret;





	crtc_state->preload_luts = glk_can_preload_luts(crtc_state);



	return 0;

	return 0;

}

}
@@ -1415,6 +1474,8 @@ static int icl_color_check(struct intel_crtc_state *crtc_state) 




	crtc_state->csc_mode = icl_csc_mode(crtc_state);

	crtc_state->csc_mode = icl_csc_mode(crtc_state);





	crtc_state->preload_luts = intel_can_preload_luts(crtc_state);



	return 0;

	return 0;

}

}

drivers/gpu/drm/i915/display/intel_ddi.c

+6 −4
Original line number Original line Diff line number Diff line
@@ -1794,10 +1794,8 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 
	 * of Color Encoding Format and Content Color Gamut] while sending

	 * of Color Encoding Format and Content Color Gamut] while sending

	 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields

	 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields

	 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.

	 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.

	 *

	 * FIXME MST doesn't pass in the conn_state

	 */

	 */

	if (conn_state && intel_dp_needs_vsc_sdp(crtc_state, conn_state))

	if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))

		temp |= DP_MSA_MISC_COLOR_VSC_SDP;

		temp |= DP_MSA_MISC_COLOR_VSC_SDP;





	I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);

	I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
@@ -3605,6 +3603,10 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, 
	else

	else

		hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state);

		hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state);





	/* MST will call a setting of MSA after an allocating of Virtual Channel

	 * from MST encoder pre_enable callback.

	 */

	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))

		intel_ddi_set_dp_msa(crtc_state, conn_state);

		intel_ddi_set_dp_msa(crtc_state, conn_state);

}

}

drivers/gpu/drm/i915/display/intel_display.c

+10 −0
Original line number Original line Diff line number Diff line
@@ -66,6 +66,7 @@ 
#include "intel_cdclk.h"

#include "intel_cdclk.h"

#include "intel_color.h"

#include "intel_color.h"

#include "intel_display_types.h"

#include "intel_display_types.h"

#include "intel_dp_link_training.h"

#include "intel_fbc.h"

#include "intel_fbc.h"

#include "intel_fbdev.h"

#include "intel_fbdev.h"

#include "intel_fifo_underrun.h"

#include "intel_fifo_underrun.h"
@@ -2528,6 +2529,9 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 
	 * the highest stride limits of them all.

	 * the highest stride limits of them all.

	 */

	 */

	crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);

	crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);

	if (!crtc)

		return 0;



	plane = to_intel_plane(crtc->base.primary);

	plane = to_intel_plane(crtc->base.primary);





	return plane->max_stride(plane, pixel_format, modifier,

	return plane->max_stride(plane, pixel_format, modifier,
@@ -14201,6 +14205,11 @@ static void intel_update_crtc(struct intel_crtc *crtc, 
		/* vblanks work again, re-enable pipe CRC. */

		/* vblanks work again, re-enable pipe CRC. */

		intel_crtc_enable_pipe_crc(crtc);

		intel_crtc_enable_pipe_crc(crtc);

	} else {

	} else {

		if (new_crtc_state->preload_luts &&

		    (new_crtc_state->base.color_mgmt_changed ||

		     new_crtc_state->update_pipe))

			intel_color_load_luts(new_crtc_state);



		intel_pre_plane_update(old_crtc_state, new_crtc_state);

		intel_pre_plane_update(old_crtc_state, new_crtc_state);





		if (new_crtc_state->update_pipe)

		if (new_crtc_state->update_pipe)
@@ -14713,6 +14722,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) 
	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {

	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {

		if (new_crtc_state->base.active &&

		if (new_crtc_state->base.active &&

		    !needs_modeset(new_crtc_state) &&

		    !needs_modeset(new_crtc_state) &&

		    !new_crtc_state->preload_luts &&

		    (new_crtc_state->base.color_mgmt_changed ||

		    (new_crtc_state->base.color_mgmt_changed ||

		     new_crtc_state->update_pipe))

		     new_crtc_state->update_pipe))

			intel_color_load_luts(new_crtc_state);

			intel_color_load_luts(new_crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

+0 −1
Original line number Original line Diff line number Diff line
@@ -27,7 +27,6 @@ 




#include <drm/drm_util.h>

#include <drm/drm_util.h>

#include <drm/i915_drm.h>

#include <drm/i915_drm.h>

#include "intel_dp_link_training.h"





enum link_m_n_set;

enum link_m_n_set;

struct dpll;

struct dpll;

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