Commit 789c4aea authored Nov 13, 2019 by Gwan-gyeong Mun Committed by Joonas Lahtinen Nov 13, 2019

drm/i915: Split a setting of MSA to MST and SST

The setting of MSA is done by the DDI .pre_enable() hook. And when we are
using MST, the MSA is only set to first mst stream by calling of
DDI .pre_eanble() hook. It raies issues to non-first mst streams.
Wrong MSA or missed MSA packets might show scrambled screen or wrong
screen.

This splits a setting of MSA to MST and SST cases. And In the MST case it
will call a setting of MSA after an allocating of Virtual Channel from
MST encoder pre_enable callback.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112212


Fixes: 0c06fa15 ("drm/i915/dp: Add support of BT.2020 Colorimetry to DP MSA")
Fixes: d4a415dc ("drm/i915: Fix MST oops due to MSA changes")
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191106212636.502471-1-gwan-gyeong.mun@intel.com


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
[vsyrjala: nuke spurious newline]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
(cherry picked from commit bd8c9cca)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191113125241.20547-1-ville.syrjala@linux.intel.com

parent 98ae6fb3

drivers/gpu/drm/i915/display/intel_ddi.c

+6 −4

Original line number	Diff line number	Diff line
		@@ -1794,10 +1794,8 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
		* of Color Encoding Format and Content Color Gamut] while sending
		* YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
		* which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
		*
		* FIXME MST doesn't pass in the conn_state
		*/
		if (conn_state && intel_dp_needs_vsc_sdp(crtc_state, conn_state))
		if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
		temp \|= DP_MSA_MISC_COLOR_VSC_SDP;

		I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
		@@ -3605,6 +3603,10 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
		else
		hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state);

		/* MST will call a setting of MSA after an allocating of Virtual Channel
		* from MST encoder pre_enable callback.
		*/
		if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
		intel_ddi_set_dp_msa(crtc_state, conn_state);
		}

drivers/gpu/drm/i915/display/intel_dp_mst.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -331,6 +331,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
		ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);

		intel_ddi_enable_pipe_clock(pipe_config);

		intel_ddi_set_dp_msa(pipe_config, conn_state);
		}

		static void intel_mst_enable_dp(struct intel_encoder *encoder,

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