Commit 2b50e49b authored by Sowjanya Komatineni's avatar Sowjanya Komatineni Committed by Thierry Reding
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clk: tegra: Add Tegra OSC to clock lookup 



OSC is one of the parent for Tegra PMC clocks clk_out_1, clk_out_2,
and clk_out_3.

This patch adds Tegra OSC to clock lookup.

Tested-by: default avatarDmitry Osipenko <digetx@gmail.com>
Reviewed-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 9a85eb4d

drivers/clk/tegra/clk-id.h

+1 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ enum clk_id { 
	tegra_clk_clk_m,

	tegra_clk_clk_m_div2,

	tegra_clk_clk_m_div4,

	tegra_clk_osc,

	tegra_clk_osc_div2,

	tegra_clk_osc_div4,

	tegra_clk_clk_out_1,

drivers/clk/tegra/clk-tegra-fixed.c

+5 −0
Original line number Diff line number Diff line
@@ -46,7 +46,12 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, 
		return -EINVAL;

	}



	dt_clk = tegra_lookup_dt_id(tegra_clk_osc, clks);

	if (!dt_clk)

		return 0;



	osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);

	*dt_clk = osc;



	/* osc_div2 */

	dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div2, clks);

drivers/clk/tegra/clk-tegra114.c

+2 −0
Original line number Diff line number Diff line
@@ -737,6 +737,7 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = { 
	[tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },

	[tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },

	[tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },

	[tegra_clk_osc] = { .dt_id = TEGRA114_CLK_OSC, .present = true },

	[tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },

	[tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },

	[tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
@@ -819,6 +820,7 @@ static struct tegra_devclk devclks[] __initdata = { 
	{ .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },

	{ .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },

	{ .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },

	{ .con_id = "osc", .dt_id = TEGRA114_CLK_OSC },

	{ .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },

	{ .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },

	{ .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },

drivers/clk/tegra/clk-tegra124.c

+2 −0
Original line number Diff line number Diff line
@@ -862,6 +862,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { 
	[tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },

	[tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },

	[tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },

	[tegra_clk_osc] = { .dt_id = TEGRA124_CLK_OSC, .present = true },

	[tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },

	[tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },

	[tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
@@ -945,6 +946,7 @@ static struct tegra_devclk devclks[] __initdata = { 
	{ .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },

	{ .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },

	{ .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },

	{ .con_id = "osc", .dt_id = TEGRA124_CLK_OSC },

	{ .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },

	{ .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },

	{ .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },

drivers/clk/tegra/clk-tegra210.c

+2 −0
Original line number Diff line number Diff line
@@ -2373,6 +2373,7 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { 
	[tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },

	[tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },

	[tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },

	[tegra_clk_osc] = { .dt_id = TEGRA210_CLK_OSC, .present = true },

	[tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true },

	[tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true },

	[tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
@@ -2501,6 +2502,7 @@ static struct tegra_devclk devclks[] __initdata = { 
	{ .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },

	{ .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },

	{ .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },

	{ .con_id = "osc", .dt_id = TEGRA210_CLK_OSC },

	{ .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 },

	{ .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 },

	{ .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },

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