Commit 9a85eb4d authored by Sowjanya Komatineni's avatar Sowjanya Komatineni Committed by Thierry Reding
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clk: tegra: Add support for OSC_DIV fixed clocks 



Tegra30 through Tegra210 has OSC_DIV2 and OSC_DIV4 fixed clocks
from the OSC pads.

This patch adds support for these clocks.

Tested-by: default avatarDmitry Osipenko <digetx@gmail.com>
Reviewed-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 5e7322bb

drivers/clk/tegra/clk-id.h

+2 −0
Original line number Diff line number Diff line
@@ -46,6 +46,8 @@ enum clk_id { 
	tegra_clk_clk_m,

	tegra_clk_clk_m_div2,

	tegra_clk_clk_m_div4,

	tegra_clk_osc_div2,

	tegra_clk_osc_div4,

	tegra_clk_clk_out_1,

	tegra_clk_clk_out_1_mux,

	tegra_clk_clk_out_2,

drivers/clk/tegra/clk-tegra-fixed.c

+16 −0
Original line number Diff line number Diff line
@@ -48,6 +48,22 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, 


	osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);



	/* osc_div2 */

	dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div2, clks);

	if (dt_clk) {

		clk = clk_register_fixed_factor(NULL, "osc_div2", "osc",

						0, 1, 2);

		*dt_clk = clk;

	}



	/* osc_div4 */

	dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div4, clks);

	if (dt_clk) {

		clk = clk_register_fixed_factor(NULL, "osc_div4", "osc",

						0, 1, 4);

		*dt_clk = clk;

	}



	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);

	if (!dt_clk)

		return 0;

drivers/clk/tegra/clk-tegra114.c

+4 −0
Original line number Diff line number Diff line
@@ -737,6 +737,8 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = { 
	[tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },

	[tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },

	[tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },

	[tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },

	[tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },

	[tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },

	[tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },

	[tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
@@ -817,6 +819,8 @@ static struct tegra_devclk devclks[] __initdata = { 
	{ .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },

	{ .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },

	{ .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },

	{ .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },

	{ .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },

	{ .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },

	{ .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },

	{ .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },

drivers/clk/tegra/clk-tegra124.c

+4 −0
Original line number Diff line number Diff line
@@ -862,6 +862,8 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { 
	[tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },

	[tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },

	[tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },

	[tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },

	[tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },

	[tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },

	[tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },

	[tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
@@ -943,6 +945,8 @@ static struct tegra_devclk devclks[] __initdata = { 
	{ .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },

	{ .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },

	{ .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },

	{ .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },

	{ .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },

	{ .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },

	{ .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },

	{ .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },

drivers/clk/tegra/clk-tegra210.c

+4 −0
Original line number Diff line number Diff line
@@ -2373,6 +2373,8 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { 
	[tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },

	[tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },

	[tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },

	[tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true },

	[tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true },

	[tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },

	[tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true },

	[tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true },
@@ -2499,6 +2501,8 @@ static struct tegra_devclk devclks[] __initdata = { 
	{ .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },

	{ .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },

	{ .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },

	{ .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 },

	{ .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 },

	{ .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },

	{ .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 },

	{ .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 },

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