Commit 2ab58c85 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'qcom-arm64-for-5.1' of... 

Merge tag 'qcom-arm64-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into arm/dt

Qualcomm ARM64 Updates for v5.1

* Add MSM8998 RPMCC, I2C, and USB related nodes
* Add MSM8996 rpmpd node
* Fix typo in MSM8996 pin definitions
* Disable MSM8996 VFE smmu to fix security violation
* Add I2C, SPI, rpmcc, uart, and WCN3990 wlan nodes on QCS404
* Enable SDCC1 HS400 support on QCS404
* Add a multitude of nodes on SDM845:
  SD, UFS, USB, LPASS, SCM, QSPI, PDC, DPU, videocc, GPU, RPMh
  bus interconnect, WCN3990 WLAN
* Add gpio ranges to SDM845 TLMM
* Fix regulator load on sdcard on MSM8998-mtp board

* tag 'qcom-arm64-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux

: (41 commits)
  arm64: dts: sdm845: Add interconnect provider DT nodes
  arm64: dts: qcom: msm8996: Disabled VFE SMMU
  arm64: dts: qcom: qcs404: Add rpmcc node
  arm64: dts: qcom: msm8998: Add rpmcc node
  arm64: dts: qcom: msm8998: Add USB-related nodes
  arm64: dts: qcom: qcs404: Add QUP I2C and SPI nodes
  arm64: dts: qcom: qcs404: Define remaining UARTs
  arm64: dts: qcom: qcs404: Specify pinctrl state for UART
  arm64: dts: qcom: sdm845: Fix lpasscc reg
  arm64: dts: qcom: sdm845: Remove the duplicate header inclusion
  arm64: dts: qcom: sdm845: Add reserve-memory nodes
  arm64: dts: qcom: sdm845: Add gpio-ranges to TLMM node
  arm64: dts: qcom: sdm845: Extend ranges and describe DMA space
  arm64: dts: qcom: sdm845: Increase address and size cells for soc
  arm64: dts: sdm845: Add rpmh powercontroller node
  arm64: dts: msm8996: Add rpmpd device node
  arm64: dts: sdm845: Add WCN3990 WLAN module device node
  arm64: dts: qcom: sdm845: Add PDC Global reset driver node
  arm64: dts: qcom: sdm845: Add SCM DT node
  arm64: dts: qcom: sdm845: Fix pcs_misc region address for UNI PHY
  ...

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 2a434f24 5e820489

arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -644,6 +644,8 @@ 
	l11 {

		regulator-min-microvolt = <1750000>;

		regulator-max-microvolt = <3337000>;

		regulator-allow-set-load;

		regulator-system-load = <200000>;

	};



	l12 {

arch/arm64/boot/dts/qcom/msm8996-pins.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -139,7 +139,7 @@ 
		};



		pinconf {

			pins = "gpio4", "gpiio5", "gpio6", "gpio7";

			pins = "gpio4", "gpio5", "gpio6", "gpio7";

			drive-strength = <2>;

			bias-disable;

		};

arch/arm64/boot/dts/qcom/msm8996.dtsi

+36 −2
Original line number Diff line number Diff line
@@ -306,6 +306,40 @@ 
				#clock-cells = <1>;

			};



			rpmpd: power-controller {

				compatible = "qcom,msm8996-rpmpd";

				#power-domain-cells = <1>;

				operating-points-v2 = <&rpmpd_opp_table>;



				rpmpd_opp_table: opp-table {

					compatible = "operating-points-v2";



					rpmpd_opp1: opp1 {

						opp-level = <1>;

					};



					rpmpd_opp2: opp2 {

						opp-level = <2>;

					};



					rpmpd_opp3: opp3 {

						opp-level = <3>;

					};



					rpmpd_opp4: opp4 {

						opp-level = <4>;

					};



					rpmpd_opp5: opp5 {

						opp-level = <5>;

					};



					rpmpd_opp6: opp6 {

						opp-level = <6>;

					};

				};

			};



			pm8994-regulators {

				compatible = "qcom,rpm-pm8994-regulators";
@@ -404,7 +438,7 @@ 
		};



		intc: interrupt-controller@9bc0000 {

			compatible = "arm,gic-v3";

			compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";

			#interrupt-cells = <3>;

			interrupt-controller;

			#redistributor-regions = <1>;
@@ -966,7 +1000,7 @@ 
			clock-names = "iface",

				      "bus";

			#iommu-cells = <1>;

			status = "ok";

			status = "disabled";

		};



		camss: camss@a00000 {

arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -65,6 +65,13 @@ 
	status = "okay";

};



&qusb2phy {

	status = "okay";



	vdda-pll-supply = <&vreg_l12a_1p8>;

	vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;

};



&rpm_requests {

	pm8998-regulators {

		compatible = "qcom,rpm-pm8998-regulators";
@@ -192,6 +199,8 @@ 
		vreg_l21a_2p95: l21 {

			regulator-min-microvolt = <2960000>;

			regulator-max-microvolt = <2960000>;

			regulator-allow-set-load;

			regulator-system-load = <800000>;

		};

		vreg_l22a_2p85: l22 {

			regulator-min-microvolt = <2864000>;
@@ -257,3 +266,18 @@ 
	pinctrl-0 = <&sdc2_clk_on  &sdc2_cmd_on  &sdc2_data_on  &sdc2_cd_on>;

	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;

};



&usb3 {

	status = "okay";

};



&usb3_dwc3 {

	dr_mode = "host"; /* Force to host until we have Type-C hooked up */

};



&usb3phy {

	status = "okay";



	vdda-phy-supply = <&vreg_l1a_0p875>;

	vdda-pll-supply = <&vreg_l2a_1p2>;

};

arch/arm64/boot/dts/qcom/msm8998.dtsi

+278 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 


#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,gcc-msm8998.h>

#include <dt-bindings/clock/qcom,rpmcc.h>

#include <dt-bindings/gpio/gpio.h>



/ {
@@ -266,6 +267,11 @@ 
		rpm_requests: rpm-requests {

			compatible = "qcom,rpm-msm8998";

			qcom,glink-channels = "rpm_requests";



			rpmcc: clock-controller {

				compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";

				#clock-cells = <1>;

			};

		};

	};
@@ -540,6 +546,11 @@ 
			reg = <0x780000 0x621c>;

			#address-cells = <1>;

			#size-cells = <1>;



			qusb2_hstx_trim: hstx-trim@423a {

				reg = <0x423a 0x1>;

				bits = <0 4>;

			};

		};



		gcc: clock-controller@100000 {
@@ -607,6 +618,93 @@ 
			#mbox-cells = <1>;

		};



		usb3: usb@a8f8800 {

			compatible = "qcom,msm8998-dwc3", "qcom,dwc3";

			reg = <0x0a8f8800 0x400>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,

				 <&gcc GCC_USB30_MASTER_CLK>,

				 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,

				 <&gcc GCC_USB30_MOCK_UTMI_CLK>,

				 <&gcc GCC_USB30_SLEEP_CLK>;

			clock-names = "cfg_noc", "core", "iface", "mock_utmi",

				      "sleep";



			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,

					  <&gcc GCC_USB30_MASTER_CLK>;

			assigned-clock-rates = <19200000>, <120000000>;



			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hs_phy_irq", "ss_phy_irq";



			power-domains = <&gcc USB_30_GDSC>;



			resets = <&gcc GCC_USB_30_BCR>;



			usb3_dwc3: dwc3@a800000 {

				compatible = "snps,dwc3";

				reg = <0x0a800000 0xcd00>;

				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;

				snps,dis_u2_susphy_quirk;

				snps,dis_enblslpm_quirk;

				phys = <&qusb2phy>, <&usb1_ssphy>;

				phy-names = "usb2-phy", "usb3-phy";

				snps,has-lpm-erratum;

				snps,hird-threshold = /bits/ 8 <0x10>;

			};

		};



		usb3phy: phy@c010000 {

			compatible = "qcom,msm8998-qmp-usb3-phy";

			reg = <0x0c010000 0x18c>;

			status = "disabled";

			#clock-cells = <1>;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,

				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,

				 <&gcc GCC_USB3_CLKREF_CLK>;

			clock-names = "aux", "cfg_ahb", "ref";



			resets = <&gcc GCC_USB3_PHY_BCR>,

				 <&gcc GCC_USB3PHY_PHY_BCR>;

			reset-names = "phy", "common";



			usb1_ssphy: lane@c010200 {

				reg = <0xc010200 0x128>,

				      <0xc010400 0x200>,

				      <0xc010c00 0x20c>,

				      <0xc010600 0x128>,

				      <0xc010800 0x200>;

				#phy-cells = <0>;

				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;

				clock-names = "pipe0";

				clock-output-names = "usb3_phy_pipe_clk_src";

			};

		};



		qusb2phy: phy@c012000 {

			compatible = "qcom,msm8998-qusb2-phy";

			reg = <0x0c012000 0x2a8>;

			status = "disabled";

			#phy-cells = <0>;



			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,

				 <&gcc GCC_RX1_USB2_CLKREF_CLK>;

			clock-names = "cfg_ahb", "ref";



			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;



			nvmem-cells = <&qusb2_hstx_trim>;

		};



		sdhc2: sdhci@c0a4900 {

			compatible = "qcom,sdhci-msm-v4";

			reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>;
@@ -624,6 +722,186 @@ 
			status = "disabled";

		};



		blsp1_i2c1: i2c@c175000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x0c175000 0x600>;

			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;



			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		blsp1_i2c2: i2c@c176000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x0c176000 0x600>;

			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;



			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		blsp1_i2c3: i2c@c177000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x0c177000 0x600>;

			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;



			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		blsp1_i2c4: i2c@c178000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x0c178000 0x600>;

			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;



			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		blsp1_i2c5: i2c@c179000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x0c179000 0x600>;

			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;



			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		blsp1_i2c6: i2c@c17a000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x0c17a000 0x600>;

			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;



			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		blsp2_i2c0: i2c@c1b5000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x0c1b5000 0x600>;

			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP2_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;



			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		blsp2_i2c1: i2c@c1b6000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x0c1b6000 0x600>;

			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP2_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;



			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		blsp2_i2c2: i2c@c1b7000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x0c1b7000 0x600>;

			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP2_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;



			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		blsp2_i2c3: i2c@c1b8000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x0c1b8000 0x600>;

			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP2_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;



			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		blsp2_i2c4: i2c@c1b9000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x0c1b9000 0x600>;

			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP2_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;



			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		blsp2_i2c5: i2c@c1ba000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x0c175000 0x600>;

			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP2_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency = <400000>;



			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		blsp2_uart1: serial@c1b0000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0xc1b0000 0x1000>;

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