Merge branches 'ib-from-asoc-3.16', 'ib-from-pm-3.16',...

stage. Just pass the values to this function, and the unsigned int

index returns the number of the frequency table entry which contains

the frequency the CPU shall be set to.

The following macros can be used as iterators over cpufreq_frequency_table:

cpufreq_for_each_entry(pos, table) - iterates over all entries of frequency

table.

cpufreq-for_each_valid_entry(pos, table) - iterates over all entries,

excluding CPUFREQ_ENTRY_INVALID frequencies.

Use arguments "pos" - a cpufreq_frequency_table * as a loop cursor and

"table" - the cpufreq_frequency_table * you want to iterate over.

For example:

	struct cpufreq_frequency_table *pos, *driver_freq_table;

	cpufreq_for_each_entry(pos, driver_freq_table) {

		/* Do something with pos */

		pos->frequency = ...

	}

- fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used

Sub-nodes:

- codec: Contain the Audio Codec node.

  - adc-port: Contain PMIC SSI port number used for ADC.

  - dac-port: Contain PMIC SSI port number used for DAC.

- leds : Contain the led nodes and initial register values in property

  "led-control". Number of register depends of used IC, for MC13783 is 6,

  for MC13892 is 4, for MC34708 is 1. See datasheet for bits definitions of

static int da850_round_armrate(struct clk *clk, unsigned long rate)

{

	int i, ret = 0, diff;

	int ret = 0, diff;

	unsigned int best = (unsigned int) -1;

	struct cpufreq_frequency_table *table = cpufreq_info.freq_table;

	struct cpufreq_frequency_table *pos;

	rate /= 1000; /* convert to kHz */

	for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {

		diff = table[i].frequency - rate;

	cpufreq_for_each_entry(pos, table) {

		diff = pos->frequency - rate;

		if (diff < 0)

			diff = -diff;

		if (diff < best) {

			best = diff;

			ret = table[i].frequency;

			ret = pos->frequency;

		}

	}

static bool is_offset_valid;

static u8 smps_offset;

/*

 * Flag to ensure Smartreflex bit in TWL

 * being cleared in board file is not overwritten.

 */

static bool __initdata twl_sr_enable_autoinit;

#define TWL4030_DCDC_GLOBAL_CFG        0x06

#define REG_SMPS_OFFSET         0xE0

#define SMARTREFLEX_ENABLE     BIT(3)

static unsigned long twl4030_vsel_to_uv(const u8 vsel)

{

	if (!cpu_is_omap34xx())

		return -ENODEV;

	/*

	 * The smartreflex bit on twl4030 specifies if the setting of voltage

	 * is done over the I2C_SR path. Since this setting is independent of

	 * the actual usage of smartreflex AVS module, we enable TWL SR bit

	 * by default irrespective of whether smartreflex AVS module is enabled

	 * on the OMAP side or not. This is because without this bit enabled,

	 * the voltage scaling through vp forceupdate/bypass mechanism of

	 * voltage scaling will not function on TWL over I2C_SR.

	 */

	if (!twl_sr_enable_autoinit)

		omap3_twl_set_sr_bit(true);

	voltdm = voltdm_lookup("mpu_iva");

	omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);

	return 0;

}

/**

 * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL

 * @enable: enable SR mode in twl or not

 *

 * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure

 * voltage scaling through OMAP SR works. Else, the smartreflex bit

 * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but

 * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct

 * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,

 * in those scenarios this bit is to be cleared (enable = false).

 *

 * Returns 0 on success, error is returned if I2C read/write fails.

 */

int __init omap3_twl_set_sr_bit(bool enable)

{

	u8 temp;

	int ret;

	if (twl_sr_enable_autoinit)

		pr_warning("%s: unexpected multiple calls\n", __func__);

	ret = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp,

			      TWL4030_DCDC_GLOBAL_CFG);

	if (ret)

		goto err;

	if (enable)

		temp |= SMARTREFLEX_ENABLE;

	else

		temp &= ~SMARTREFLEX_ENABLE;

	ret = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp,

			       TWL4030_DCDC_GLOBAL_CFG);

	if (!ret) {

		twl_sr_enable_autoinit = true;

		return 0;

	}

err:

	pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);

	return ret;

}

static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data)

{

	int i;

	struct cpufreq_frequency_table *pos;

	struct acpi_processor_performance *perf;

	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)

	perf = data->acpi_data;

	for (i = 0; data->freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {

		if (msr == perf->states[data->freq_table[i].driver_data].status)

			return data->freq_table[i].frequency;

	}

	cpufreq_for_each_entry(pos, data->freq_table)

		if (msr == perf->states[pos->driver_data].status)

			return pos->frequency;

	return data->freq_table[0].frequency;

}