Commit 25831571 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/virtualization' into next 

* pci/virtualization:
  PCI: Add comments about ROM BAR updating
  PCI: Decouple IORESOURCE_ROM_ENABLE and PCI_ROM_ADDRESS_ENABLE
  PCI: Remove pci_resource_bar() and pci_iov_resource_bar()
  PCI: Don't update VF BARs while VF memory space is enabled
  PCI: Separate VF BAR updates from standard BAR updates
  PCI: Update BARs using property bits appropriate for type
  PCI: Ignore BAR updates on virtual functions
  PCI: Do any VF BAR updates before enabling the BARs
  PCI: Support INTx masking on ConnectX-4 with firmware x.14.1100+
  PCI: Convert Mellanox broken INTx quirks to be for listed devices only
  PCI: Convert broken INTx masking quirks from HEADER to FINAL
  net/mlx4_core: Use device ID defines
  PCI: Add Mellanox device IDs
parents daaed104 0b457dde

drivers/net/ethernet/mellanox/mlx4/main.c

+43 −41
Original line number Diff line number Diff line
@@ -4012,49 +4012,51 @@ int mlx4_restart_one(struct pci_dev *pdev) 
	return err;

}



#define MLX_SP(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_FORCE_SENSE_PORT }

#define MLX_VF(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_IS_VF }

#define MLX_GN(id) { PCI_VDEVICE(MELLANOX, id), 0 }



static const struct pci_device_id mlx4_pci_table[] = {

	/* MT25408 "Hermon" SDR */

	{ PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },

	/* MT25408 "Hermon" DDR */

	{ PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },

	/* MT25408 "Hermon" QDR */

	{ PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },

	/* MT25408 "Hermon" DDR PCIe gen2 */

	{ PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },

	/* MT25408 "Hermon" QDR PCIe gen2 */

	{ PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },

	/* MT25408 "Hermon" EN 10GigE */

	{ PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },

	/* MT25408 "Hermon" EN 10GigE PCIe gen2 */

	{ PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },

	/* MT25458 ConnectX EN 10GBASE-T 10GigE */

	{ PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },

	/* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */

	{ PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },

	/* MT26468 ConnectX EN 10GigE PCIe gen2*/

	{ PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },

	/* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */

	{ PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },

	/* MT26478 ConnectX2 40GigE PCIe gen2 */

	{ PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },

	/* MT25400 Family [ConnectX-2 Virtual Function] */

	{ PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },

	/* MT25408 "Hermon" */

	MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_SDR),	/* SDR */

	MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR),	/* DDR */

	MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR),	/* QDR */

	MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2), /* DDR Gen2 */

	MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2),	/* QDR Gen2 */

	MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN),	/* EN 10GigE */

	MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2),  /* EN 10GigE Gen2 */

	/* MT25458 ConnectX EN 10GBASE-T */

	MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN),

	MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2),	/* Gen2 */

	/* MT26468 ConnectX EN 10GigE PCIe Gen2*/

	MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2),

	/* MT26438 ConnectX EN 40GigE PCIe Gen2 5GT/s */

	MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2),

	/* MT26478 ConnectX2 40GigE PCIe Gen2 */

	MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX2),

	/* MT25400 Family [ConnectX-2] */

	MLX_VF(0x1002),					/* Virtual Function */

	/* MT27500 Family [ConnectX-3] */

	{ PCI_VDEVICE(MELLANOX, 0x1003), 0 },

	/* MT27500 Family [ConnectX-3 Virtual Function] */

	{ PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },

	{ PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */

	{ PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */

	{ PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */

	{ PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */

	{ PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */

	{ PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */

	{ PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */

	{ PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */

	{ PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */

	{ PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */

	{ PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */

	{ PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */

	MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3),

	MLX_VF(0x1004),					/* Virtual Function */

	MLX_GN(0x1005),					/* MT27510 Family */

	MLX_GN(0x1006),					/* MT27511 Family */

	MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO),	/* MT27520 Family */

	MLX_GN(0x1008),					/* MT27521 Family */

	MLX_GN(0x1009),					/* MT27530 Family */

	MLX_GN(0x100a),					/* MT27531 Family */

	MLX_GN(0x100b),					/* MT27540 Family */

	MLX_GN(0x100c),					/* MT27541 Family */

	MLX_GN(0x100d),					/* MT27550 Family */

	MLX_GN(0x100e),					/* MT27551 Family */

	MLX_GN(0x100f),					/* MT27560 Family */

	MLX_GN(0x1010),					/* MT27561 Family */



	/*

	 * See the mellanox_check_broken_intx_masking() quirk when

	 * adding devices

	 */



	{ 0, }

};

drivers/pci/iov.c

+55 −15
Original line number Diff line number Diff line
@@ -306,13 +306,6 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn) 
			return rc;

	}



	pci_iov_set_numvfs(dev, nr_virtfn);

	iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;

	pci_cfg_access_lock(dev);

	pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);

	msleep(100);

	pci_cfg_access_unlock(dev);



	iov->initial_VFs = initial;

	if (nr_virtfn < initial)

		initial = nr_virtfn;
@@ -323,6 +316,13 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn) 
		goto err_pcibios;

	}



	pci_iov_set_numvfs(dev, nr_virtfn);

	iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;

	pci_cfg_access_lock(dev);

	pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);

	msleep(100);

	pci_cfg_access_unlock(dev);



	for (i = 0; i < initial; i++) {

		rc = pci_iov_add_virtfn(dev, i, 0);

		if (rc)
@@ -554,21 +554,61 @@ void pci_iov_release(struct pci_dev *dev) 
}



/**

 * pci_iov_resource_bar - get position of the SR-IOV BAR

 * pci_iov_update_resource - update a VF BAR

 * @dev: the PCI device

 * @resno: the resource number

 *

 * Returns position of the BAR encapsulated in the SR-IOV capability.

 * Update a VF BAR in the SR-IOV capability of a PF.

 */

int pci_iov_resource_bar(struct pci_dev *dev, int resno)

void pci_iov_update_resource(struct pci_dev *dev, int resno)

{

	if (resno < PCI_IOV_RESOURCES || resno > PCI_IOV_RESOURCE_END)

		return 0;

	struct pci_sriov *iov = dev->is_physfn ? dev->sriov : NULL;

	struct resource *res = dev->resource + resno;

	int vf_bar = resno - PCI_IOV_RESOURCES;

	struct pci_bus_region region;

	u16 cmd;

	u32 new;

	int reg;



	/*

	 * The generic pci_restore_bars() path calls this for all devices,

	 * including VFs and non-SR-IOV devices.  If this is not a PF, we

	 * have nothing to do.

	 */

	if (!iov)

		return;



	BUG_ON(!dev->is_physfn);

	pci_read_config_word(dev, iov->pos + PCI_SRIOV_CTRL, &cmd);

	if ((cmd & PCI_SRIOV_CTRL_VFE) && (cmd & PCI_SRIOV_CTRL_MSE)) {

		dev_WARN(&dev->dev, "can't update enabled VF BAR%d %pR\n",

			 vf_bar, res);

		return;

	}



	return dev->sriov->pos + PCI_SRIOV_BAR +

		4 * (resno - PCI_IOV_RESOURCES);

	/*

	 * Ignore unimplemented BARs, unused resource slots for 64-bit

	 * BARs, and non-movable resources, e.g., those described via

	 * Enhanced Allocation.

	 */

	if (!res->flags)

		return;



	if (res->flags & IORESOURCE_UNSET)

		return;



	if (res->flags & IORESOURCE_PCI_FIXED)

		return;



	pcibios_resource_to_bus(dev->bus, &region, res);

	new = region.start;

	new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;



	reg = iov->pos + PCI_SRIOV_BAR + 4 * vf_bar;

	pci_write_config_dword(dev, reg, new);

	if (res->flags & IORESOURCE_MEM_64) {

		new = region.start >> 16 >> 16;

		pci_write_config_dword(dev, reg + 4, new);

	}

}



resource_size_t __weak pcibios_iov_resource_alignment(struct pci_dev *dev,

drivers/pci/pci.c

+0 −34
Original line number Diff line number Diff line
@@ -564,10 +564,6 @@ static void pci_restore_bars(struct pci_dev *dev) 
{

	int i;



	/* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */

	if (dev->is_virtfn)

		return;



	for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)

		pci_update_resource(dev, i);

}
@@ -4831,36 +4827,6 @@ int pci_select_bars(struct pci_dev *dev, unsigned long flags) 
}

EXPORT_SYMBOL(pci_select_bars);



/**

 * pci_resource_bar - get position of the BAR associated with a resource

 * @dev: the PCI device

 * @resno: the resource number

 * @type: the BAR type to be filled in

 *

 * Returns BAR position in config space, or 0 if the BAR is invalid.

 */

int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)

{

	int reg;



	if (resno < PCI_ROM_RESOURCE) {

		*type = pci_bar_unknown;

		return PCI_BASE_ADDRESS_0 + 4 * resno;

	} else if (resno == PCI_ROM_RESOURCE) {

		*type = pci_bar_mem32;

		return dev->rom_base_reg;

	} else if (resno < PCI_BRIDGE_RESOURCES) {

		/* device specific resource */

		*type = pci_bar_unknown;

		reg = pci_iov_resource_bar(dev, resno);

		if (reg)

			return reg;

	}



	dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);

	return 0;

}



/* Some architectures require additional programming to enable VGA */

static arch_set_vga_state_t arch_set_vga_state;

drivers/pci/pci.h

+1 −6
Original line number Diff line number Diff line
@@ -242,7 +242,6 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 
int pci_setup_device(struct pci_dev *dev);

int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,

		    struct resource *res, unsigned int reg);

int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type);

void pci_configure_ari(struct pci_dev *dev);

void __pci_bus_size_bridges(struct pci_bus *bus,

			struct list_head *realloc_head);
@@ -286,7 +285,7 @@ static inline void pci_restore_ats_state(struct pci_dev *dev) 
#ifdef CONFIG_PCI_IOV

int pci_iov_init(struct pci_dev *dev);

void pci_iov_release(struct pci_dev *dev);

int pci_iov_resource_bar(struct pci_dev *dev, int resno);

void pci_iov_update_resource(struct pci_dev *dev, int resno);

resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);

void pci_restore_iov_state(struct pci_dev *dev);

int pci_iov_bus_range(struct pci_bus *bus);
@@ -300,10 +299,6 @@ static inline void pci_iov_release(struct pci_dev *dev) 


{

}

static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno)

{

	return 0;

}

static inline void pci_restore_iov_state(struct pci_dev *dev)

{

}

drivers/pci/probe.c

+2 −1
Original line number Diff line number Diff line
@@ -227,7 +227,8 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 
			mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;

		}

	} else {

		res->flags |= (l & IORESOURCE_ROM_ENABLE);

		if (l & PCI_ROM_ADDRESS_ENABLE)

			res->flags |= IORESOURCE_ROM_ENABLE;

		l64 = l & PCI_ROM_ADDRESS_MASK;

		sz64 = sz & PCI_ROM_ADDRESS_MASK;

		mask64 = (u32)PCI_ROM_ADDRESS_MASK;

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