Commit 1e8955fd authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

PCI/ASPM: Pass L1SS Capabilities value, not struct aspm_register_info 

aspm_calc_l1ss_info() needs only the L1SS Capabilities.  It doesn't need
anything else from struct aspm_register_info, so pass only the Capabilities
value.  No functional change intended.

Link: https://lore.kernel.org/r/20201015193039.12585-11-helgaas@kernel.org


Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 28a1488e

drivers/pci/pcie/aspm.c

+8 −9
Original line number Diff line number Diff line
@@ -476,8 +476,7 @@ static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos, 


/* Calculate L1.2 PM substate timing parameters */

static void aspm_calc_l1ss_info(struct pcie_link_state *link,

				struct aspm_register_info *upreg,

				struct aspm_register_info *dwreg)

				u32 parent_l1ss_cap, u32 child_l1ss_cap)

{

	struct pci_dev *child = link->downstream, *parent = link->pdev;

	u32 val1, val2, scale1, scale2;
@@ -489,15 +488,15 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, 
		return;



	/* Choose the greater of the two Port Common_Mode_Restore_Times */

	val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;

	val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;

	val1 = (parent_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;

	val2 = (child_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;

	t_common_mode = max(val1, val2);



	/* Choose the greater of the two Port T_POWER_ON times */

	val1   = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;

	scale1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;

	val2   = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;

	scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;

	val1   = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;

	scale1 = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;

	val2   = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;

	scale2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;



	if (calc_l1ss_pwron(parent, scale1, val1) >

	    calc_l1ss_pwron(child, scale2, val2)) {
@@ -624,7 +623,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) 
		link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;



	if (link->aspm_support & ASPM_STATE_L1SS)

		aspm_calc_l1ss_info(link, &upreg, &dwreg);

		aspm_calc_l1ss_info(link, upreg.l1ss_cap, dwreg.l1ss_cap);



	/* Save default state */

	link->aspm_default = link->aspm_enabled;

CRA Git | Maintained and supported by SUSTech CRA and CCSE