Commit 28a1488e authored by Saheed O. Bolarinwa's avatar Saheed O. Bolarinwa Committed by Bjorn Helgaas
Browse files

PCI/ASPM: Remove struct aspm_register_info.l1ss_ctl1 

Previously we stored the L1SS Control 1 register in the struct
aspm_register_info.

We only need this information in one place, so read it there and remove it
from struct aspm_register_info.  No functional change intended.

[bhelgaas: split ctl1/ctl2]
Link: https://lore.kernel.org/r/20201015193039.12585-10-helgaas@kernel.org


Signed-off-by: default avatarSaheed O. Bolarinwa <refactormyself@gmail.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 81c2b807

drivers/pci/pcie/aspm.c

+14 −12
Original line number Diff line number Diff line
@@ -385,27 +385,21 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) 
struct aspm_register_info {

	/* L1 substates */

	u32 l1ss_cap;

	u32 l1ss_ctl1;

};



static void pcie_get_aspm_reg(struct pci_dev *pdev,

			      struct aspm_register_info *info)

{

	/* Read L1 PM substate capabilities */

	info->l1ss_cap = info->l1ss_ctl1 = 0;

	info->l1ss_cap = 0;



	if (!pdev->l1ss)

		return;



	pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CAP,

			      &info->l1ss_cap);

	if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) {

	if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))

		info->l1ss_cap = 0;

		return;

	}



	pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1,

			      &info->l1ss_ctl1);

}



static void pcie_aspm_check_latency(struct pci_dev *endpoint)
@@ -534,6 +528,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) 
	struct pci_dev *child = link->downstream, *parent = link->pdev;

	u32 parent_lnkcap, child_lnkcap;

	u16 parent_lnkctl, child_lnkctl;

	u32 parent_l1ss_ctl1 = 0, child_l1ss_ctl1 = 0;

	struct pci_bus *linkbus = parent->subordinate;

	struct aspm_register_info upreg, dwreg;
@@ -612,13 +607,20 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) 
	if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)

		link->aspm_support |= ASPM_STATE_L1_2_PCIPM;



	if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)

	if (upreg.l1ss_cap)

		pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,

				      &parent_l1ss_ctl1);

	if (dwreg.l1ss_cap)

		pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1,

				      &child_l1ss_ctl1);



	if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)

		link->aspm_enabled |= ASPM_STATE_L1_1;

	if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)

	if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)

		link->aspm_enabled |= ASPM_STATE_L1_2;

	if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)

	if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)

		link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;

	if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)

	if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)

		link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;



	if (link->aspm_support & ASPM_STATE_L1SS)

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