Commit 1e41a766 authored by Tony W Wang-oc's avatar Tony W Wang-oc Committed by Thomas Gleixner
Browse files

x86/speculation/spectre_v2: Exclude Zhaoxin CPUs from SPECTRE_V2 



New Zhaoxin family 7 CPUs are not affected by SPECTRE_V2. So define a
separate cpu_vuln_whitelist bit NO_SPECTRE_V2 and add these CPUs to the cpu
vulnerability whitelist.

Signed-off-by: default avatarTony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/1579227872-26972-2-git-send-email-TonyWWang-oc@zhaoxin.com
parent 5efc6fa9

arch/x86/kernel/cpu/common.c

+8 −1
Original line number Diff line number Diff line
@@ -1023,6 +1023,7 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 
#define MSBDS_ONLY		BIT(5)

#define NO_SWAPGS		BIT(6)

#define NO_ITLB_MULTIHIT	BIT(7)

#define NO_SPECTRE_V2		BIT(8)



#define VULNWL(_vendor, _family, _model, _whitelist)	\

	{ X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist }
@@ -1084,6 +1085,10 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 
	/* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */

	VULNWL_AMD(X86_FAMILY_ANY,	NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),

	VULNWL_HYGON(X86_FAMILY_ANY,	NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),



	/* Zhaoxin Family 7 */

	VULNWL(CENTAUR,	7, X86_MODEL_ANY,	NO_SPECTRE_V2),

	VULNWL(ZHAOXIN,	7, X86_MODEL_ANY,	NO_SPECTRE_V2),

	{}

};
@@ -1116,6 +1121,8 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 
		return;



	setup_force_cpu_bug(X86_BUG_SPECTRE_V1);



	if (!cpu_matches(NO_SPECTRE_V2))

		setup_force_cpu_bug(X86_BUG_SPECTRE_V2);



	if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) &&

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