Commit 5efc6fa9 authored Jan 10, 2020 by Pawan Gupta Committed by Thomas Gleixner Jan 17, 2020

x86/cpu: Update cached HLE state on write to TSX_CTRL_CPUID_CLEAR



/proc/cpuinfo currently reports Hardware Lock Elision (HLE) feature to
be present on boot cpu even if it was disabled during the bootup. This
is because cpuinfo_x86->x86_capability HLE bit is not updated after TSX
state is changed via the new MSR IA32_TSX_CTRL.

Update the cached HLE bit also since it is expected to change after an
update to CPUID_CLEAR bit in MSR IA32_TSX_CTRL.

Fixes: 95c5824f ("x86/cpu: Add a "tsx=" cmdline option with TSX disabled by default")
Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Neelima Krishnan <neelima.krishnan@intel.com>
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/2529b99546294c893dfa1c89e2b3e46da3369a59.1578685425.git.pawan.kumar.gupta@linux.intel.com

parent b3a987b0

arch/x86/kernel/cpu/tsx.c

+7 −6

Original line number	Diff line number	Diff line
		@@ -115,11 +115,12 @@ void __init tsx_init(void)
		tsx_disable();

		/*
		* tsx_disable() will change the state of the
		* RTM CPUID bit. Clear it here since it is now
		* expected to be not set.
		* tsx_disable() will change the state of the RTM and HLE CPUID
		* bits. Clear them here since they are now expected to be not
		* set.
		*/
		setup_clear_cpu_cap(X86_FEATURE_RTM);
		setup_clear_cpu_cap(X86_FEATURE_HLE);
		} else if (tsx_ctrl_state == TSX_CTRL_ENABLE) {

		/*
		@@ -131,10 +132,10 @@ void __init tsx_init(void)
		tsx_enable();

		/*
		* tsx_enable() will change the state of the
		* RTM CPUID bit. Force it here since it is now
		* expected to be set.
		* tsx_enable() will change the state of the RTM and HLE CPUID
		* bits. Force them here since they are now expected to be set.
		*/
		setup_force_cpu_cap(X86_FEATURE_RTM);
		setup_force_cpu_cap(X86_FEATURE_HLE);
		}
		}

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