Commit 1de143cc authored by Pankaj Bharadiya's avatar Pankaj Bharadiya Committed by Jani Nikula
Browse files

drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available 



drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.

Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.

The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.

@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_device *T = ...;
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}

@rule2@
identifier func, T;
@@
func(struct drm_device *T,...) {
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}

@rule3@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}

@rule4@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}

Signed-off-by: default avatarPankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200220165507.16823-3-pankaj.laxminarayan.bharadiya@intel.com
parent aff35110

drivers/gpu/drm/i915/display/intel_ddi.c

+51 −41
Original line number Diff line number Diff line
@@ -1006,18 +1006,18 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder) 
		intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);

		default_entry = 6;

	} else {

		WARN(1, "ddi translation table missing\n");

		drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n");

		return 0;

	}



	if (WARN_ON_ONCE(n_entries == 0))

	if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0))

		return 0;



	level = intel_bios_hdmi_level_shift(encoder);

	if (level < 0)

		level = default_entry;



	if (WARN_ON_ONCE(level >= n_entries))

	if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))

		level = n_entries - 1;



	return level;
@@ -1075,9 +1075,9 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 


	ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);



	if (WARN_ON_ONCE(!ddi_translations))

	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))

		return;

	if (WARN_ON_ONCE(level >= n_entries))

	if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))

		level = n_entries - 1;



	/* If we're boosting the current, set bit 31 of trans1 */
@@ -1208,7 +1208,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, 
	/* Configure Port Clock Select */

	ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);

	intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel);

	WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);

	drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL);



	/* Start the training iterating through available voltages and emphasis,

	 * testing each value twice. */
@@ -1317,7 +1317,8 @@ intel_ddi_get_crtc_encoder(struct intel_crtc *crtc) 
	}



	if (num_encoders != 1)

		WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,

		drm_WARN(dev, 1, "%d encoders on crtc for pipe %c\n",

			 num_encoders,

			 pipe_name(crtc->pipe));



	BUG_ON(ret == NULL);
@@ -1476,7 +1477,7 @@ int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, 
	dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>

		      DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;



	if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))

	if (drm_WARN_ON(&dev_priv->drm, p0 == 0 || p1 == 0 || p2 == 0))

		return 0;



	return dco_freq / (p0 * p1 * p2 * 5);
@@ -1664,7 +1665,7 @@ static void cnl_ddi_clock_get(struct intel_encoder *encoder, 
			link_clock = 405000;

			break;

		default:

			WARN(1, "Unsupported link rate\n");

			drm_WARN(&dev_priv->drm, 1, "Unsupported link rate\n");

			break;

		}

		link_clock *= 2;
@@ -1756,12 +1757,12 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder, 
		else if (pll == SPLL_FREQ_2700MHz)

			link_clock = 270000;

		else {

			WARN(1, "bad spll freq\n");

			drm_WARN(&dev_priv->drm, 1, "bad spll freq\n");

			return;

		}

		break;

	default:

		WARN(1, "bad port clock sel\n");

		drm_WARN(&dev_priv->drm, 1, "bad port clock sel\n");

		return;

	}
@@ -1822,7 +1823,7 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 
	if (!intel_crtc_has_dp_encoder(crtc_state))

		return;



	WARN_ON(transcoder_is_dsi(cpu_transcoder));

	drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));



	temp = DP_MSA_MISC_SYNC_CLOCK;
@@ -1845,7 +1846,7 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 
	}



	/* nonsense combination */

	WARN_ON(crtc_state->limited_color_range &&

	drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&

		    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);



	if (crtc_state->limited_color_range)
@@ -1962,7 +1963,8 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state) 
			enum transcoder master;



			master = crtc_state->mst_master_transcoder;

			WARN_ON(master == INVALID_TRANSCODER);

			drm_WARN_ON(&dev_priv->drm,

				    master == INVALID_TRANSCODER);

			temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);

		}

	} else {
@@ -2043,10 +2045,11 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, 


	wakeref = intel_display_power_get_if_enabled(dev_priv,

						     intel_encoder->power_domain);

	if (WARN_ON(!wakeref))

	if (drm_WARN_ON(dev, !wakeref))

		return -ENXIO;



	if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {

	if (drm_WARN_ON(dev,

			!intel_encoder->get_hw_state(intel_encoder, &pipe))) {

		ret = -EIO;

		goto out;

	}
@@ -2283,7 +2286,8 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 
	 * happen since fake-MST encoders don't set their get_power_domains()

	 * hook.

	 */

	if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))

	if (drm_WARN_ON(&dev_priv->drm,

			intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))

		return;



	dig_port = enc_to_dig_port(encoder);
@@ -2381,9 +2385,9 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, 
		else

			ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);



		if (WARN_ON_ONCE(!ddi_translations))

		if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))

			return;

		if (WARN_ON_ONCE(level >= n_entries))

		if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))

			level = n_entries - 1;



		iboost = ddi_translations[level].i_boost;
@@ -2416,9 +2420,9 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 
	else

		ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);



	if (WARN_ON_ONCE(!ddi_translations))

	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))

		return;

	if (WARN_ON_ONCE(level >= n_entries))

	if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))

		level = n_entries - 1;



	bxt_ddi_phy_set_signal_level(dev_priv, port,
@@ -2468,9 +2472,10 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) 
			intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);

	}



	if (WARN_ON(n_entries < 1))

	if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))

		n_entries = 1;

	if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))

	if (drm_WARN_ON(&dev_priv->drm,

			n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))

		n_entries = ARRAY_SIZE(index_to_dp_signal_levels);



	return index_to_dp_signal_levels[n_entries - 1] &
@@ -2513,9 +2518,9 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 
	else

		ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);



	if (WARN_ON_ONCE(!ddi_translations))

	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))

		return;

	if (WARN_ON_ONCE(level >= n_entries))

	if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))

		level = n_entries - 1;



	/* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
@@ -3047,7 +3052,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, 
	mutex_lock(&dev_priv->dpll_lock);



	val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);

	WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);

	drm_WARN_ON(&dev_priv->drm,

		    (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);



	if (intel_phy_is_combo(dev_priv, phy)) {

		/*
@@ -3106,7 +3112,7 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, 
		 * Punt on the case now where clock is gated, but it would

		 * be needed by the port. Something else is really broken then.

		 */

		if (WARN_ON(ddi_clk_needed))

		if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))

			continue;



		DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
@@ -3138,7 +3144,7 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 
		 * In the unlikely case that BIOS enables DP in MST mode, just

		 * warn since our MST HW readout is incomplete.

		 */

		if (WARN_ON(is_mst))

		if (drm_WARN_ON(&dev_priv->drm, is_mst))

			return;

	}
@@ -3157,7 +3163,8 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 
			if (other_encoder == encoder)

				continue;



			if (WARN_ON(port_mask & BIT(other_encoder->port)))

			if (drm_WARN_ON(&dev_priv->drm,

					port_mask & BIT(other_encoder->port)))

				return;

		}

		/*
@@ -3179,7 +3186,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, 
	u32 val;

	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;



	if (WARN_ON(!pll))

	if (drm_WARN_ON(&dev_priv->drm, !pll))

		return;



	mutex_lock(&dev_priv->dpll_lock);
@@ -3285,7 +3292,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, 


	switch (pin_assignment) {

	case 0x0:

		WARN_ON(intel_dig_port->tc_mode != TC_PORT_LEGACY);

		drm_WARN_ON(&dev_priv->drm,

			    intel_dig_port->tc_mode != TC_PORT_LEGACY);

		if (width == 1) {

			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;

		} else {
@@ -3542,9 +3550,10 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder, 
	int level = intel_ddi_dp_level(intel_dp);



	if (INTEL_GEN(dev_priv) < 11)

		WARN_ON(is_mst && (port == PORT_A || port == PORT_E));

		drm_WARN_ON(&dev_priv->drm,

			    is_mst && (port == PORT_A || port == PORT_E));

	else

		WARN_ON(is_mst && port == PORT_A);

		drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);



	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,

				 crtc_state->lane_count, is_mst);
@@ -3683,7 +3692,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder, 
	 *   the DP link parameteres

	 */



	WARN_ON(crtc_state->has_pch_encoder);

	drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);



	if (INTEL_GEN(dev_priv) >= 11)

		icl_map_plls_to_ports(encoder, crtc_state);
@@ -3958,9 +3967,9 @@ gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 
		[PORT_E] = TRANSCODER_A,

	};



	WARN_ON(INTEL_GEN(dev_priv) < 9);

	drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9);



	if (WARN_ON(port < PORT_A || port > PORT_E))

	if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))

		port = PORT_A;



	return CHICKEN_TRANS(trans[port]);
@@ -4258,7 +4267,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, 
	u32 temp, flags = 0;



	/* XXX: DSI transcoder paranoia */

	if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))

	if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))

		return;



	intel_dsc_get_config(encoder, pipe_config);
@@ -4661,7 +4670,8 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, 


	crtc_state = to_intel_crtc_state(crtc->base.state);



	WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));

	drm_WARN_ON(&dev_priv->drm,

		    !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));



	if (!crtc_state->hw.active)

		return 0;
@@ -4913,7 +4923,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 
		encoder->update_complete = intel_ddi_update_complete;

	}



	WARN_ON(port > PORT_I);

	drm_WARN_ON(&dev_priv->drm, port > PORT_I);

	intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +

					      port - PORT_A;

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