Commit aff35110 authored by Pankaj Bharadiya's avatar Pankaj Bharadiya Committed by Jani Nikula
Browse files

drm/i915/display/cdclk: Make WARN* drm specific where drm_priv ptr is available 



drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.

Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_i915_private struct pointer is
readily available.

The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.

@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}

@rule2@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}

Signed-off-by: default avatarPankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200220165507.16823-2-pankaj.laxminarayan.bharadiya@intel.com
parent 2713eb41

drivers/gpu/drm/i915/display/intel_cdclk.c

+48 −36
Original line number Diff line number Diff line
@@ -525,7 +525,8 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) 
	 * FIXME is this guaranteed to clear

	 * immediately or should we poll for it?

	 */

	WARN_ON(intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND);

	drm_WARN_ON(&dev_priv->drm,

		    intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND);

}



static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
@@ -727,7 +728,8 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 
	u32 val;

	int ret;



	if (WARN((intel_de_read(dev_priv, LCPLL_CTL) &

	if (drm_WARN(&dev_priv->drm,

		     (intel_de_read(dev_priv, LCPLL_CTL) &

		      (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |

		       LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |

		       LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
@@ -842,12 +844,13 @@ static void skl_dpll0_update(struct drm_i915_private *dev_priv, 
	if ((val & LCPLL_PLL_ENABLE) == 0)

		return;



	if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))

	if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0))

		return;



	val = intel_de_read(dev_priv, DPLL_CTRL1);



	if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |

	if (drm_WARN_ON(&dev_priv->drm,

			(val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |

				DPLL_CTRL1_SSC(SKL_DPLL0) |

				DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=

			DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
@@ -952,7 +955,7 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) 
{

	u32 val;



	WARN_ON(vco != 8100000 && vco != 8640000);

	drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);



	/*

	 * We always enable DPLL0 with the lowest link rate possible, but still
@@ -1017,7 +1020,8 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, 
	 * use the corresponding VCO freq as that always leads to using the

	 * minimum 308MHz CDCLK.

	 */

	WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000);

	drm_WARN_ON_ONCE(&dev_priv->drm,

			 IS_SKYLAKE(dev_priv) && vco == 8640000);



	ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,

				SKL_CDCLK_PREPARE_FOR_CHANGE,
@@ -1032,8 +1036,9 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, 
	/* Choose frequency for this cdclk */

	switch (cdclk) {

	default:

		WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);

		WARN_ON(vco != 0);

		drm_WARN_ON(&dev_priv->drm,

			    cdclk != dev_priv->cdclk.hw.bypass);

		drm_WARN_ON(&dev_priv->drm, vco != 0);

		/* fall through */

	case 308571:

	case 337500:
@@ -1235,7 +1240,8 @@ static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 
		    table[i].cdclk >= min_cdclk)

			return table[i].cdclk;



	WARN(1, "Cannot satisfy minimum cdclk %d with refclk %u\n",

	drm_WARN(&dev_priv->drm, 1,

		 "Cannot satisfy minimum cdclk %d with refclk %u\n",

		 min_cdclk, dev_priv->cdclk.hw.ref);

	return 0;

}
@@ -1253,7 +1259,7 @@ static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) 
		    table[i].cdclk == cdclk)

			return dev_priv->cdclk.hw.ref * table[i].ratio;



	WARN(1, "cdclk %d not valid for refclk %u\n",

	drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",

		 cdclk, dev_priv->cdclk.hw.ref);

	return 0;

}
@@ -1399,7 +1405,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 
		div = 2;

		break;

	case BXT_CDCLK_CD2X_DIV_SEL_1_5:

		WARN(IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,

		drm_WARN(&dev_priv->drm,

			 IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,

			 "Unsupported divider\n");

		div = 3;

		break;
@@ -1407,7 +1414,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 
		div = 4;

		break;

	case BXT_CDCLK_CD2X_DIV_SEL_4:

		WARN(INTEL_GEN(dev_priv) >= 10, "Unsupported divider\n");

		drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10,

			 "Unsupported divider\n");

		div = 8;

		break;

	default:
@@ -1547,14 +1555,16 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 
	/* cdclk = vco / 2 / div{1,1.5,2,4} */

	switch (DIV_ROUND_CLOSEST(vco, cdclk)) {

	default:

		WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);

		WARN_ON(vco != 0);

		drm_WARN_ON(&dev_priv->drm,

			    cdclk != dev_priv->cdclk.hw.bypass);

		drm_WARN_ON(&dev_priv->drm, vco != 0);

		/* fall through */

	case 2:

		divider = BXT_CDCLK_CD2X_DIV_SEL_1;

		break;

	case 3:

		WARN(IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,

		drm_WARN(&dev_priv->drm,

			 IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,

			 "Unsupported divider\n");

		divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;

		break;
@@ -1562,7 +1572,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 
		divider = BXT_CDCLK_CD2X_DIV_SEL_2;

		break;

	case 8:

		WARN(INTEL_GEN(dev_priv) >= 10, "Unsupported divider\n");

		drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10,

			 "Unsupported divider\n");

		divider = BXT_CDCLK_CD2X_DIV_SEL_4;

		break;

	}
@@ -1860,14 +1871,15 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, 
	if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))

		return;



	if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))

	if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk))

		return;



	intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");



	dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);



	if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),

	if (drm_WARN(&dev_priv->drm,

		     intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),

		     "cdclk state doesn't match!\n")) {

		intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]");

		intel_dump_cdclk_config(cdclk_config, "[sw state]");
@@ -1897,7 +1909,7 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 


	if (pipe == INVALID_PIPE ||

	    old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {

		WARN_ON(!new_cdclk_state->base.changed);

		drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);



		intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);

	}
@@ -1926,7 +1938,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 


	if (pipe != INVALID_PIPE &&

	    old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {

		WARN_ON(!new_cdclk_state->base.changed);

		drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);



		intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);

	}
@@ -2550,7 +2562,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) 
		int max_cdclk, vco;



		vco = dev_priv->skl_preferred_vco_freq;

		WARN_ON(vco != 8100000 && vco != 8640000);

		drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);



		/*

		 * Use the lower (vco 8640) cdclk values as a
@@ -2809,7 +2821,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 
	else if (IS_I845G(dev_priv))

		dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;

	else { /* 830 */

		WARN(!IS_I830(dev_priv),

		drm_WARN(&dev_priv->drm, !IS_I830(dev_priv),

			 "Unknown platform. Assuming 133 MHz CDCLK\n");

		dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;

	}

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