Commit 1d2686d4 authored by Hersen Wu's avatar Hersen Wu Committed by Alex Deucher
Browse files

drm/amdgpu/powerplay: nv1x, renior copy dcn clock settings of watermark to smu during boot up 



dc to pplib interface is changed for navi1x, renoir.
display_config_changed is not called by dc anymore.
smu_write_watermarks_table is not executed for navi1x, renoir
during boot up.

solution: call smu_write_watermarks_table just after dc pass
watermark clock settings to pplib

Signed-off-by: default avatarHersen Wu <hersenxs.wu@amd.com>
Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f1c2cd3f

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

+5 −2
Original line number Diff line number Diff line
@@ -2006,9 +2006,12 @@ int smu_set_watermarks_for_clock_ranges(struct smu_context *smu, 
			smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&

			smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {

		smu_set_watermarks_table(smu, table, clock_ranges);



		if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {

			smu->watermarks_bitmap |= WATERMARKS_EXIST;

			smu->watermarks_bitmap &= ~WATERMARKS_LOADED;

		}

	}



	mutex_unlock(&smu->mutex);

drivers/gpu/drm/amd/powerplay/navi10_ppt.c

+13 −9
Original line number Diff line number Diff line
@@ -1062,15 +1062,6 @@ static int navi10_display_config_changed(struct smu_context *smu) 
{

	int ret = 0;



	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&

	    !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {

		ret = smu_write_watermarks_table(smu);

		if (ret)

			return ret;



		smu->watermarks_bitmap |= WATERMARKS_LOADED;

	}



	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&

	    smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&

	    smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
@@ -1493,6 +1484,7 @@ static int navi10_set_watermarks_table(struct smu_context *smu, 
				       *clock_ranges)

{

	int i;

	int ret = 0;

	Watermarks_t *table = watermarks;



	if (!table || !clock_ranges)
@@ -1544,6 +1536,18 @@ static int navi10_set_watermarks_table(struct smu_context *smu, 
				clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;

	}



	smu->watermarks_bitmap |= WATERMARKS_EXIST;



	/* pass data to smu controller */

	if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {

		ret = smu_write_watermarks_table(smu);

		if (ret) {

			pr_err("Failed to update WMTABLE!");

			return ret;

		}

		smu->watermarks_bitmap |= WATERMARKS_LOADED;

	}



	return 0;

}

drivers/gpu/drm/amd/powerplay/renoir_ppt.c

+3 −2
Original line number Diff line number Diff line
@@ -806,9 +806,10 @@ static int renoir_set_watermarks_table( 
				clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;

	}



	smu->watermarks_bitmap |= WATERMARKS_EXIST;



	/* pass data to smu controller */

	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&

			!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {

	if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {

		ret = smu_write_watermarks_table(smu);

		if (ret) {

			pr_err("Failed to update WMTABLE!");

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