drm/amdgpu: correct ROM_INDEX/DATA offset for VEGA20 (f1c2cd3f) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/soc15.c

+23 −2

Original line number	Diff line number	Diff line
		@@ -89,6 +89,13 @@
		#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
		#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
		#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0

		/* for Vega20/arcturus regiter offset change */
		#define mmROM_INDEX_VG20 0x00e4
		#define mmROM_INDEX_VG20_BASE_IDX 0
		#define mmROM_DATA_VG20 0x00e5
		#define mmROM_DATA_VG20_BASE_IDX 0

		/*
		* Indirect registers accessor
		*/
		@@ -309,6 +316,8 @@ static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
		{
		u32 *dw_ptr;
		u32 i, length_dw;
		uint32_t rom_index_offset;
		uint32_t rom_data_offset;

		if (bios == NULL)
		return false;
		@@ -321,11 +330,23 @@ static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
		dw_ptr = (u32 *)bios;
		length_dw = ALIGN(length_bytes, 4) / 4;

		switch (adev->asic_type) {
		case CHIP_VEGA20:
		case CHIP_ARCTURUS:
		rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX_VG20);
		rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA_VG20);
		break;
		default:
		rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
		rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
		break;
		}

		/* set rom index to 0 */
		WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
		WREG32(rom_index_offset, 0);
		/* read out the rom data */
		for (i = 0; i < length_dw; i++)
		dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
		dw_ptr[i] = RREG32(rom_data_offset);

		return true;
		}