Commit 1cf65c45 authored by Christian König's avatar Christian König
Browse files

drm/ttm: add caching state to ttm_bus_placement 



And implement setting it up correctly in the drivers.

This allows getting rid of the placement flags for this.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarMichael J. Ruhl <michael.j.ruhl@intel.com>
Link: https://patchwork.freedesktop.org/patch/394254/
parent 1b4ea4c5

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

+1 −0
Original line number Diff line number Diff line
@@ -769,6 +769,7 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso 


		mem->bus.offset += adev->gmc.aper_base;

		mem->bus.is_iomem = true;

		mem->bus.caching = ttm_write_combined;

		break;

	default:

		return -EINVAL;

drivers/gpu/drm/drm_gem_vram_helper.c

+1 −0
Original line number Diff line number Diff line
@@ -981,6 +981,7 @@ static int bo_driver_io_mem_reserve(struct ttm_bo_device *bdev, 
	case TTM_PL_VRAM:

		mem->bus.offset = (mem->start << PAGE_SHIFT) + vmm->vram_base;

		mem->bus.is_iomem = true;

		mem->bus.caching = ttm_write_combined;

		break;

	default:

		return -EINVAL;

drivers/gpu/drm/nouveau/nouveau_bo.c

+11 −0
Original line number Diff line number Diff line
@@ -1134,6 +1134,8 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *reg) 
	struct nouveau_drm *drm = nouveau_bdev(bdev);

	struct nvkm_device *device = nvxx_device(&drm->client.device);

	struct nouveau_mem *mem = nouveau_mem(reg);

	struct nvif_mmu *mmu = &drm->client.mmu;

	const u8 type = mmu->type[drm->ttm.type_vram].type;

	int ret;



	mutex_lock(&drm->ttm.io_reserve_mutex);
@@ -1149,6 +1151,7 @@ retry: 
			reg->bus.offset = (reg->start << PAGE_SHIFT) +

				drm->agp.base;

			reg->bus.is_iomem = !drm->agp.cma;

			reg->bus.caching = ttm_write_combined;

		}

#endif

		if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 ||
@@ -1162,6 +1165,14 @@ retry: 
		reg->bus.offset = (reg->start << PAGE_SHIFT) +

			device->func->resource_addr(device, 1);

		reg->bus.is_iomem = true;



		/* Some BARs do not support being ioremapped WC */

		if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&

		    type & NVIF_MEM_UNCACHED)

			reg->bus.caching = ttm_uncached;

		else

			reg->bus.caching = ttm_write_combined;



		if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {

			union {

				struct nv50_mem_map_v0 nv50;

drivers/gpu/drm/qxl/qxl_ttm.c

+2 −0
Original line number Diff line number Diff line
@@ -83,11 +83,13 @@ int qxl_ttm_io_mem_reserve(struct ttm_bo_device *bdev, 
	case TTM_PL_VRAM:

		mem->bus.is_iomem = true;

		mem->bus.offset = (mem->start << PAGE_SHIFT) + qdev->vram_base;

		mem->bus.caching = ttm_cached;

		break;

	case TTM_PL_PRIV:

		mem->bus.is_iomem = true;

		mem->bus.offset = (mem->start << PAGE_SHIFT) +

			qdev->surfaceram_base;

		mem->bus.caching = ttm_cached;

		break;

	default:

		return -EINVAL;

drivers/gpu/drm/radeon/radeon_ttm.c

+2 −0
Original line number Diff line number Diff line
@@ -372,6 +372,7 @@ static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso 
			mem->bus.offset = (mem->start << PAGE_SHIFT) +

				rdev->mc.agp_base;

			mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;

			mem->bus.caching = ttm_write_combined;

		}

#endif

		break;
@@ -382,6 +383,7 @@ static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso 
			return -EINVAL;

		mem->bus.offset += rdev->mc.aper_base;

		mem->bus.is_iomem = true;

		mem->bus.caching = ttm_write_combined;

#ifdef __alpha__

		/*

		 * Alpha: use bus.addr to hold the ioremap() return,

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