Commit 1b4ea4c5 authored by Christian König's avatar Christian König
Browse files

drm/ttm: set the tt caching state at creation time 



All drivers can determine the tt caching state at creation time,
no need to do this on the fly during every validation.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarMichael J. Ruhl <michael.j.ruhl@intel.com>
Link: https://patchwork.freedesktop.org/patch/394253/
parent 070c7fa5

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

+1 −1
Original line number Diff line number Diff line
@@ -124,7 +124,7 @@ uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo) 
	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);

	struct ttm_dma_tt *ttm;



	if (bo->num_pages != 1 || bo->ttm->caching_state == tt_cached)

	if (bo->num_pages != 1 || bo->ttm->caching == ttm_cached)

		return AMDGPU_BO_INVALID_OFFSET;



	ttm = container_of(bo->ttm, struct ttm_dma_tt, ttm);

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

+9 −2
Original line number Diff line number Diff line
@@ -1292,7 +1292,9 @@ static void amdgpu_ttm_backend_destroy(struct ttm_bo_device *bdev, 
static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,

					   uint32_t page_flags)

{

	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);

	struct amdgpu_ttm_tt *gtt;

	enum ttm_caching caching;



	gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);

	if (gtt == NULL) {
@@ -1300,8 +1302,13 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 
	}

	gtt->gobj = &bo->base;



	if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)

		caching = ttm_write_combined;

	else

		caching = ttm_cached;



	/* allocate space for the uninitialized page entries */

	if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {

	if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {

		kfree(gtt);

		return NULL;

	}
@@ -1525,7 +1532,7 @@ uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 
	if (mem && mem->mem_type == TTM_PL_TT) {

		flags |= AMDGPU_PTE_SYSTEM;



		if (ttm->caching_state == tt_cached)

		if (ttm->caching == ttm_cached)

			flags |= AMDGPU_PTE_SNOOPED;

	}

drivers/gpu/drm/drm_gem_vram_helper.c

+1 −1
Original line number Diff line number Diff line
@@ -918,7 +918,7 @@ static struct ttm_tt *bo_driver_ttm_tt_create(struct ttm_buffer_object *bo, 
	if (!tt)

		return NULL;



	ret = ttm_tt_init(tt, bo, page_flags);

	ret = ttm_tt_init(tt, bo, page_flags, ttm_cached);

	if (ret < 0)

		goto err_ttm_tt_init;

drivers/gpu/drm/nouveau/nouveau_sgdma.c

+12 −1
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
#include "nouveau_drv.h"

#include "nouveau_mem.h"

#include "nouveau_ttm.h"

#include "nouveau_bo.h"



struct nouveau_sgdma_be {

	/* this has to be the first field so populate/unpopulated in
@@ -67,13 +68,23 @@ nouveau_sgdma_unbind(struct ttm_bo_device *bdev, struct ttm_tt *ttm) 
struct ttm_tt *

nouveau_sgdma_create_ttm(struct ttm_buffer_object *bo, uint32_t page_flags)

{

	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);

	struct nouveau_bo *nvbo = nouveau_bo(bo);

	struct nouveau_sgdma_be *nvbe;

	enum ttm_caching caching;



	if (nvbo->force_coherent)

		caching = ttm_uncached;

	else if (drm->agp.bridge)

		caching = ttm_write_combined;

	else

		caching = ttm_cached;



	nvbe = kzalloc(sizeof(*nvbe), GFP_KERNEL);

	if (!nvbe)

		return NULL;



	if (ttm_dma_tt_init(&nvbe->ttm, bo, page_flags)) {

	if (ttm_dma_tt_init(&nvbe->ttm, bo, page_flags, caching)) {

		kfree(nvbe);

		return NULL;

	}

drivers/gpu/drm/qxl/qxl_ttm.c

+1 −1
Original line number Diff line number Diff line
@@ -133,7 +133,7 @@ static struct ttm_tt *qxl_ttm_tt_create(struct ttm_buffer_object *bo, 
	ttm = kzalloc(sizeof(struct ttm_tt), GFP_KERNEL);

	if (ttm == NULL)

		return NULL;

	if (ttm_tt_init(ttm, bo, page_flags)) {

	if (ttm_tt_init(ttm, bo, page_flags, ttm_cached)) {

		kfree(ttm);

		return NULL;

	}

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