Commit 1c5c1b5d authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
Browse files

Merge branch 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm 

Pull ARM cpufreq driver changes for 5.4 from Viresh Kumar:

"This contains:

- Minor fixes for mediatek driver (Andrew-sh.Cheng and Fabien Parent).
- Minor updates for imx driver (Anson Huang).
- Minor fix for ti-cpufreq driver (Gustavo A. R. Silva).
- Minor fix for ap806 driver (Hariprasad Kelam).
- Significant updates to qcom cpufreq drivers, mostly to support CPR
  stuff (Jorge Ramirez-Ortiz, Niklas Cassel, Sibi Sankar, Douglas
  RAILLARD and Sricharan R).
- New sun50i cpufreq driver (Yangtao Li).

It also contains a few OPP changes which were required because of
dependencies for the qcom cpufreq changes."

* 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm: (22 commits)
  cpufreq: Add qcs404 to cpufreq-dt-platdev blacklist
  cpufreq: qcom: Add support for qcs404 on nvmem driver
  cpufreq: qcom: Refactor the driver to make it easier to extend
  cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs
  dt-bindings: opp: Add qcom-opp bindings with properties needed for CPR
  dt-bindings: opp: qcom-nvmem: Support pstates provided by a power domain
  cpufreq: mediatek: Add support for mt8183
  cpufreq: mediatek: change to regulator_get_optional
  cpufreq: imx-cpufreq-dt: Add i.MX8MN support
  cpufreq: Use imx-cpufreq-dt for i.MX8MN's speed grading
  cpufreq: qcom-hw: invoke frequency-invariance setter function
  cpufreq: qcom-hw: Update logic to detect turbo frequency
  cpufreq: mediatek-cpufreq: Add compatible for MT8516
  cpufreq: ti-cpufreq: Mark expected switch fall-through
  dt-bindings: opp: qcom-nvmem: Make speedbin related properties optional
  dt-bindings: opp: Re-organise kryo cpufreq to use it for other nvmem based qcom socs
  opp: Add dev_pm_opp_find_level_exact()
  opp: Return genpd virtual devices from dev_pm_opp_attach_genpd()
  opp: Not all power-domains are scalable
  cpufreq: ap806: Add NULL check after kcalloc
  ...
parents beb4e08e f75d2acc

Documentation/devicetree/bindings/opp/kryo-cpufreq.txt→Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt

+121 −6
Original line number Diff line number Diff line 
Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings

Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings

===================================



In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996

that have KRYO processors, the CPU ferequencies subset and voltage value

of each OPP varies based on the silicon variant in use.

In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996,

the CPU frequencies subset and voltage value of each OPP varies based on

the silicon variant in use.

Qualcomm Technologies, Inc. Process Voltage Scaling Tables

defines the voltage and frequency value based on the msm-id in SMEM

and speedbin blown in the efuse combination.

The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC

The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC

to provide the OPP framework with required information (existing HW bitmap).

This is used to determine the voltage and frequency value for each OPP of

operating-points-v2 table when it is parsed by the OPP framework.



Required properties:

--------------------

In 'cpus' nodes:

In 'cpu' nodes:

- operating-points-v2: Phandle to the operating-points-v2 table to use.



In 'operating-points-v2' table:

- compatible: Should be

	- 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.



Optional properties:

--------------------

In 'cpu' nodes:

- power-domains: A phandle pointing to the PM domain specifier which provides

		the performance states available for active state management.

		Please refer to the power-domains bindings

		Documentation/devicetree/bindings/power/power_domain.txt

		and also examples below.

- power-domain-names: Should be

	- 'cpr' for qcs404.



In 'operating-points-v2' table:

- nvmem-cells: A phandle pointing to a nvmem-cells node representing the

		efuse registers that has information about the

		speedbin that is used to select the right frequency/voltage
@@ -678,3 +691,105 @@ soc { 
		};

	};

};



Example 2:

---------



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		CPU0: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x100>;

			....

			clocks = <&apcs_glb>;

			operating-points-v2 = <&cpu_opp_table>;

			power-domains = <&cpr>;

			power-domain-names = "cpr";

		};



		CPU1: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x101>;

			....

			clocks = <&apcs_glb>;

			operating-points-v2 = <&cpu_opp_table>;

			power-domains = <&cpr>;

			power-domain-names = "cpr";

		};



		CPU2: cpu@102 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x102>;

			....

			clocks = <&apcs_glb>;

			operating-points-v2 = <&cpu_opp_table>;

			power-domains = <&cpr>;

			power-domain-names = "cpr";

		};



		CPU3: cpu@103 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x103>;

			....

			clocks = <&apcs_glb>;

			operating-points-v2 = <&cpu_opp_table>;

			power-domains = <&cpr>;

			power-domain-names = "cpr";

		};

	};



	cpu_opp_table: cpu-opp-table {

		compatible = "operating-points-v2-kryo-cpu";

		opp-shared;



		opp-1094400000 {

			opp-hz = /bits/ 64 <1094400000>;

			required-opps = <&cpr_opp1>;

		};

		opp-1248000000 {

			opp-hz = /bits/ 64 <1248000000>;

			required-opps = <&cpr_opp2>;

		};

		opp-1401600000 {

			opp-hz = /bits/ 64 <1401600000>;

			required-opps = <&cpr_opp3>;

		};

	};



	cpr_opp_table: cpr-opp-table {

		compatible = "operating-points-v2-qcom-level";



		cpr_opp1: opp1 {

			opp-level = <1>;

			qcom,opp-fuse-level = <1>;

		};

		cpr_opp2: opp2 {

			opp-level = <2>;

			qcom,opp-fuse-level = <2>;

		};

		cpr_opp3: opp3 {

			opp-level = <3>;

			qcom,opp-fuse-level = <3>;

		};

	};



....



soc {

....

	cpr: power-controller@b018000 {

		compatible = "qcom,qcs404-cpr", "qcom,cpr";

		reg = <0x0b018000 0x1000>;

		....

		vdd-apc-supply = <&pms405_s3>;

		#power-domain-cells = <0>;

		operating-points-v2 = <&cpr_opp_table>;

		....

	};

};

Documentation/devicetree/bindings/opp/qcom-opp.txt

0 → 100644
+19 −0
Original line number Diff line number Diff line 
Qualcomm OPP bindings to describe OPP nodes



The bindings are based on top of the operating-points-v2 bindings

described in Documentation/devicetree/bindings/opp/opp.txt

Additional properties are described below.



* OPP Table Node



Required properties:

- compatible: Allow OPPs to express their compatibility. It should be:

  "operating-points-v2-qcom-level"



* OPP Node



Required properties:

- qcom,opp-fuse-level: A positive value representing the fuse corner/level

  associated with this OPP node. Sometimes several corners/levels shares

  a certain fuse corner/level. A fuse corner/level contains e.g. ref uV,

  min uV, and max uV.

Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt

0 → 100644
+167 −0
Original line number Diff line number Diff line 
Allwinner Technologies, Inc. NVMEM CPUFreq and OPP bindings

===================================



For some SoCs, the CPU frequency subset and voltage value of each OPP

varies based on the silicon variant in use. Allwinner Process Voltage

Scaling Tables defines the voltage and frequency value based on the

speedbin blown in the efuse combination. The sun50i-cpufreq-nvmem driver

reads the efuse value from the SoC to provide the OPP framework with

required information.



Required properties:

--------------------

In 'cpus' nodes:

- operating-points-v2: Phandle to the operating-points-v2 table to use.



In 'operating-points-v2' table:

- compatible: Should be

	- 'allwinner,sun50i-h6-operating-points'.

- nvmem-cells: A phandle pointing to a nvmem-cells node representing the

		efuse registers that has information about the speedbin

		that is used to select the right frequency/voltage value

		pair. Please refer the for nvmem-cells bindings

		Documentation/devicetree/bindings/nvmem/nvmem.txt and

		also examples below.



In every OPP node:

- opp-microvolt-<name>: Voltage in micro Volts.

			At runtime, the platform can pick a <name> and

			matching opp-microvolt-<name> property.

			[See: opp.txt]

			HW:		<name>:

			sun50i-h6	speed0 speed1 speed2



Example 1:

---------



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			compatible = "arm,cortex-a53";

			device_type = "cpu";

			reg = <0>;

			enable-method = "psci";

			clocks = <&ccu CLK_CPUX>;

			clock-latency-ns = <244144>; /* 8 32k periods */

			operating-points-v2 = <&cpu_opp_table>;

			#cooling-cells = <2>;

		};



		cpu1: cpu@1 {

			compatible = "arm,cortex-a53";

			device_type = "cpu";

			reg = <1>;

			enable-method = "psci";

			clocks = <&ccu CLK_CPUX>;

			clock-latency-ns = <244144>; /* 8 32k periods */

			operating-points-v2 = <&cpu_opp_table>;

			#cooling-cells = <2>;

		};



		cpu2: cpu@2 {

			compatible = "arm,cortex-a53";

			device_type = "cpu";

			reg = <2>;

			enable-method = "psci";

			clocks = <&ccu CLK_CPUX>;

			clock-latency-ns = <244144>; /* 8 32k periods */

			operating-points-v2 = <&cpu_opp_table>;

			#cooling-cells = <2>;

		};



		cpu3: cpu@3 {

			compatible = "arm,cortex-a53";

			device_type = "cpu";

			reg = <3>;

			enable-method = "psci";

			clocks = <&ccu CLK_CPUX>;

			clock-latency-ns = <244144>; /* 8 32k periods */

			operating-points-v2 = <&cpu_opp_table>;

			#cooling-cells = <2>;

		};

        };



        cpu_opp_table: opp_table {

                compatible = "allwinner,sun50i-h6-operating-points";

                nvmem-cells = <&speedbin_efuse>;

                opp-shared;



                opp@480000000 {

                        clock-latency-ns = <244144>; /* 8 32k periods */

                        opp-hz = /bits/ 64 <480000000>;



                        opp-microvolt-speed0 = <880000>;

                        opp-microvolt-speed1 = <820000>;

                        opp-microvolt-speed2 = <800000>;

                };



                opp@720000000 {

                        clock-latency-ns = <244144>; /* 8 32k periods */

                        opp-hz = /bits/ 64 <720000000>;



                        opp-microvolt-speed0 = <880000>;

                        opp-microvolt-speed1 = <820000>;

                        opp-microvolt-speed2 = <800000>;

                };



                opp@816000000 {

                        clock-latency-ns = <244144>; /* 8 32k periods */

                        opp-hz = /bits/ 64 <816000000>;



                        opp-microvolt-speed0 = <880000>;

                        opp-microvolt-speed1 = <820000>;

                        opp-microvolt-speed2 = <800000>;

                };



                opp@888000000 {

                        clock-latency-ns = <244144>; /* 8 32k periods */

                        opp-hz = /bits/ 64 <888000000>;



                        opp-microvolt-speed0 = <940000>;

                        opp-microvolt-speed1 = <820000>;

                        opp-microvolt-speed2 = <800000>;

                };



                opp@1080000000 {

                        clock-latency-ns = <244144>; /* 8 32k periods */

                        opp-hz = /bits/ 64 <1080000000>;



                        opp-microvolt-speed0 = <1060000>;

                        opp-microvolt-speed1 = <880000>;

                        opp-microvolt-speed2 = <840000>;

                };



                opp@1320000000 {

                        clock-latency-ns = <244144>; /* 8 32k periods */

                        opp-hz = /bits/ 64 <1320000000>;



                        opp-microvolt-speed0 = <1160000>;

                        opp-microvolt-speed1 = <940000>;

                        opp-microvolt-speed2 = <900000>;

                };



                opp@1488000000 {

                        clock-latency-ns = <244144>; /* 8 32k periods */

                        opp-hz = /bits/ 64 <1488000000>;



                        opp-microvolt-speed0 = <1160000>;

                        opp-microvolt-speed1 = <1000000>;

                        opp-microvolt-speed2 = <960000>;

                };

        };

....

soc {

....

	sid: sid@3006000 {

		compatible = "allwinner,sun50i-h6-sid";

		reg = <0x03006000 0x400>;

		#address-cells = <1>;

		#size-cells = <1>;

		....

		speedbin_efuse: speed@1c {

			reg = <0x1c 4>;

		};

        };

};

MAINTAINERS

+9 −2
Original line number Diff line number Diff line
@@ -676,6 +676,13 @@ L: linux-media@vger.kernel.org 
S:	Maintained

F:	drivers/staging/media/allegro-dvt/



ALLWINNER CPUFREQ DRIVER

M:	Yangtao Li <tiny.windzz@gmail.com>

L:	linux-pm@vger.kernel.org

S:	Maintained

F:	Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt

F:	drivers/cpufreq/sun50i-cpufreq-nvmem.c



ALLWINNER SECURITY SYSTEM

M:	Corentin Labbe <clabbe.montjoie@gmail.com>

L:	linux-crypto@vger.kernel.org
@@ -13300,8 +13307,8 @@ QUALCOMM CPUFREQ DRIVER MSM8996/APQ8096 
M:	Ilia Lin <ilia.lin@kernel.org>

L:	linux-pm@vger.kernel.org

S:	Maintained

F:	Documentation/devicetree/bindings/opp/kryo-cpufreq.txt

F:	drivers/cpufreq/qcom-cpufreq-kryo.c

F:	Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt

F:	drivers/cpufreq/qcom-cpufreq-nvmem.c



QUALCOMM EMAC GIGABIT ETHERNET DRIVER

M:	Timur Tabi <timur@kernel.org>

drivers/cpufreq/Kconfig.arm

+14 −2
Original line number Diff line number Diff line
@@ -19,6 +19,18 @@ config ACPI_CPPC_CPUFREQ 


	  If in doubt, say N.



config ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM

	tristate "Allwinner nvmem based SUN50I CPUFreq driver"

	depends on ARCH_SUNXI

	depends on NVMEM_SUNXI_SID

	select PM_OPP

	help

	  This adds the nvmem based CPUFreq driver for Allwinner

	  h6 SoC.



	  To compile this driver as a module, choose M here: the

	  module will be called sun50i-cpufreq-nvmem.



config ARM_ARMADA_37XX_CPUFREQ

	tristate "Armada 37xx CPUFreq support"

	depends on ARCH_MVEBU && CPUFREQ_DT
@@ -120,8 +132,8 @@ config ARM_OMAP2PLUS_CPUFREQ 
	depends on ARCH_OMAP2PLUS

	default ARCH_OMAP2PLUS



config ARM_QCOM_CPUFREQ_KRYO

	tristate "Qualcomm Kryo based CPUFreq"

config ARM_QCOM_CPUFREQ_NVMEM

	tristate "Qualcomm nvmem based CPUFreq"

	depends on ARM64

	depends on QCOM_QFPROM

	depends on QCOM_SMEM

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