Loading Documentation/devicetree/bindings/opp/kryo-cpufreq.txt→Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt +121 −6 Original line number Diff line number Diff line Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings =================================== In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996 that have KRYO processors, the CPU ferequencies subset and voltage value of each OPP varies based on the silicon variant in use. In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996, the CPU frequencies subset and voltage value of each OPP varies based on the silicon variant in use. Qualcomm Technologies, Inc. Process Voltage Scaling Tables defines the voltage and frequency value based on the msm-id in SMEM and speedbin blown in the efuse combination. The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC to provide the OPP framework with required information (existing HW bitmap). This is used to determine the voltage and frequency value for each OPP of operating-points-v2 table when it is parsed by the OPP framework. Required properties: -------------------- In 'cpus' nodes: In 'cpu' nodes: - operating-points-v2: Phandle to the operating-points-v2 table to use. In 'operating-points-v2' table: - compatible: Should be - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996. Optional properties: -------------------- In 'cpu' nodes: - power-domains: A phandle pointing to the PM domain specifier which provides the performance states available for active state management. Please refer to the power-domains bindings Documentation/devicetree/bindings/power/power_domain.txt and also examples below. - power-domain-names: Should be - 'cpr' for qcs404. In 'operating-points-v2' table: - nvmem-cells: A phandle pointing to a nvmem-cells node representing the efuse registers that has information about the speedbin that is used to select the right frequency/voltage Loading Loading @@ -678,3 +691,105 @@ soc { }; }; }; Example 2: --------- cpus { #address-cells = <1>; #size-cells = <0>; CPU0: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x100>; .... clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; power-domains = <&cpr>; power-domain-names = "cpr"; }; CPU1: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x101>; .... clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; power-domains = <&cpr>; power-domain-names = "cpr"; }; CPU2: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x102>; .... clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; power-domains = <&cpr>; power-domain-names = "cpr"; }; CPU3: cpu@103 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x103>; .... clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; power-domains = <&cpr>; power-domain-names = "cpr"; }; }; cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2-kryo-cpu"; opp-shared; opp-1094400000 { opp-hz = /bits/ 64 <1094400000>; required-opps = <&cpr_opp1>; }; opp-1248000000 { opp-hz = /bits/ 64 <1248000000>; required-opps = <&cpr_opp2>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; required-opps = <&cpr_opp3>; }; }; cpr_opp_table: cpr-opp-table { compatible = "operating-points-v2-qcom-level"; cpr_opp1: opp1 { opp-level = <1>; qcom,opp-fuse-level = <1>; }; cpr_opp2: opp2 { opp-level = <2>; qcom,opp-fuse-level = <2>; }; cpr_opp3: opp3 { opp-level = <3>; qcom,opp-fuse-level = <3>; }; }; .... soc { .... cpr: power-controller@b018000 { compatible = "qcom,qcs404-cpr", "qcom,cpr"; reg = <0x0b018000 0x1000>; .... vdd-apc-supply = <&pms405_s3>; #power-domain-cells = <0>; operating-points-v2 = <&cpr_opp_table>; .... }; }; Documentation/devicetree/bindings/opp/qcom-opp.txt 0 → 100644 +19 −0 Original line number Diff line number Diff line Qualcomm OPP bindings to describe OPP nodes The bindings are based on top of the operating-points-v2 bindings described in Documentation/devicetree/bindings/opp/opp.txt Additional properties are described below. * OPP Table Node Required properties: - compatible: Allow OPPs to express their compatibility. It should be: "operating-points-v2-qcom-level" * OPP Node Required properties: - qcom,opp-fuse-level: A positive value representing the fuse corner/level associated with this OPP node. Sometimes several corners/levels shares a certain fuse corner/level. A fuse corner/level contains e.g. ref uV, min uV, and max uV. MAINTAINERS +2 −2 Original line number Diff line number Diff line Loading @@ -13292,8 +13292,8 @@ QUALCOMM CPUFREQ DRIVER MSM8996/APQ8096 M: Ilia Lin <ilia.lin@kernel.org> L: linux-pm@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/opp/kryo-cpufreq.txt F: drivers/cpufreq/qcom-cpufreq-kryo.c F: Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt F: drivers/cpufreq/qcom-cpufreq-nvmem.c QUALCOMM EMAC GIGABIT ETHERNET DRIVER M: Timur Tabi <timur@kernel.org> Loading drivers/cpufreq/Kconfig.arm +2 −2 Original line number Diff line number Diff line Loading @@ -132,8 +132,8 @@ config ARM_OMAP2PLUS_CPUFREQ depends on ARCH_OMAP2PLUS default ARCH_OMAP2PLUS config ARM_QCOM_CPUFREQ_KRYO tristate "Qualcomm Kryo based CPUFreq" config ARM_QCOM_CPUFREQ_NVMEM tristate "Qualcomm nvmem based CPUFreq" depends on ARM64 depends on QCOM_QFPROM depends on QCOM_SMEM Loading drivers/cpufreq/Makefile +1 −1 Original line number Diff line number Diff line Loading @@ -64,7 +64,7 @@ obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW) += qcom-cpufreq-hw.o obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM) += qcom-cpufreq-nvmem.o obj-$(CONFIG_ARM_RASPBERRYPI_CPUFREQ) += raspberrypi-cpufreq.o obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o Loading Loading
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt→Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt +121 −6 Original line number Diff line number Diff line Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings =================================== In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996 that have KRYO processors, the CPU ferequencies subset and voltage value of each OPP varies based on the silicon variant in use. In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996, the CPU frequencies subset and voltage value of each OPP varies based on the silicon variant in use. Qualcomm Technologies, Inc. Process Voltage Scaling Tables defines the voltage and frequency value based on the msm-id in SMEM and speedbin blown in the efuse combination. The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC to provide the OPP framework with required information (existing HW bitmap). This is used to determine the voltage and frequency value for each OPP of operating-points-v2 table when it is parsed by the OPP framework. Required properties: -------------------- In 'cpus' nodes: In 'cpu' nodes: - operating-points-v2: Phandle to the operating-points-v2 table to use. In 'operating-points-v2' table: - compatible: Should be - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996. Optional properties: -------------------- In 'cpu' nodes: - power-domains: A phandle pointing to the PM domain specifier which provides the performance states available for active state management. Please refer to the power-domains bindings Documentation/devicetree/bindings/power/power_domain.txt and also examples below. - power-domain-names: Should be - 'cpr' for qcs404. In 'operating-points-v2' table: - nvmem-cells: A phandle pointing to a nvmem-cells node representing the efuse registers that has information about the speedbin that is used to select the right frequency/voltage Loading Loading @@ -678,3 +691,105 @@ soc { }; }; }; Example 2: --------- cpus { #address-cells = <1>; #size-cells = <0>; CPU0: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x100>; .... clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; power-domains = <&cpr>; power-domain-names = "cpr"; }; CPU1: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x101>; .... clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; power-domains = <&cpr>; power-domain-names = "cpr"; }; CPU2: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x102>; .... clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; power-domains = <&cpr>; power-domain-names = "cpr"; }; CPU3: cpu@103 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x103>; .... clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; power-domains = <&cpr>; power-domain-names = "cpr"; }; }; cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2-kryo-cpu"; opp-shared; opp-1094400000 { opp-hz = /bits/ 64 <1094400000>; required-opps = <&cpr_opp1>; }; opp-1248000000 { opp-hz = /bits/ 64 <1248000000>; required-opps = <&cpr_opp2>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; required-opps = <&cpr_opp3>; }; }; cpr_opp_table: cpr-opp-table { compatible = "operating-points-v2-qcom-level"; cpr_opp1: opp1 { opp-level = <1>; qcom,opp-fuse-level = <1>; }; cpr_opp2: opp2 { opp-level = <2>; qcom,opp-fuse-level = <2>; }; cpr_opp3: opp3 { opp-level = <3>; qcom,opp-fuse-level = <3>; }; }; .... soc { .... cpr: power-controller@b018000 { compatible = "qcom,qcs404-cpr", "qcom,cpr"; reg = <0x0b018000 0x1000>; .... vdd-apc-supply = <&pms405_s3>; #power-domain-cells = <0>; operating-points-v2 = <&cpr_opp_table>; .... }; };
Documentation/devicetree/bindings/opp/qcom-opp.txt 0 → 100644 +19 −0 Original line number Diff line number Diff line Qualcomm OPP bindings to describe OPP nodes The bindings are based on top of the operating-points-v2 bindings described in Documentation/devicetree/bindings/opp/opp.txt Additional properties are described below. * OPP Table Node Required properties: - compatible: Allow OPPs to express their compatibility. It should be: "operating-points-v2-qcom-level" * OPP Node Required properties: - qcom,opp-fuse-level: A positive value representing the fuse corner/level associated with this OPP node. Sometimes several corners/levels shares a certain fuse corner/level. A fuse corner/level contains e.g. ref uV, min uV, and max uV.
MAINTAINERS +2 −2 Original line number Diff line number Diff line Loading @@ -13292,8 +13292,8 @@ QUALCOMM CPUFREQ DRIVER MSM8996/APQ8096 M: Ilia Lin <ilia.lin@kernel.org> L: linux-pm@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/opp/kryo-cpufreq.txt F: drivers/cpufreq/qcom-cpufreq-kryo.c F: Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt F: drivers/cpufreq/qcom-cpufreq-nvmem.c QUALCOMM EMAC GIGABIT ETHERNET DRIVER M: Timur Tabi <timur@kernel.org> Loading
drivers/cpufreq/Kconfig.arm +2 −2 Original line number Diff line number Diff line Loading @@ -132,8 +132,8 @@ config ARM_OMAP2PLUS_CPUFREQ depends on ARCH_OMAP2PLUS default ARCH_OMAP2PLUS config ARM_QCOM_CPUFREQ_KRYO tristate "Qualcomm Kryo based CPUFreq" config ARM_QCOM_CPUFREQ_NVMEM tristate "Qualcomm nvmem based CPUFreq" depends on ARM64 depends on QCOM_QFPROM depends on QCOM_SMEM Loading
drivers/cpufreq/Makefile +1 −1 Original line number Diff line number Diff line Loading @@ -64,7 +64,7 @@ obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW) += qcom-cpufreq-hw.o obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM) += qcom-cpufreq-nvmem.o obj-$(CONFIG_ARM_RASPBERRYPI_CPUFREQ) += raspberrypi-cpufreq.o obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o Loading
