Commit 1c3a4540 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'hisi-arm64-dt-for-5.2' of git://github.com/hisilicon/linux-hisi into arm/dt 

ARM64: DT: Hisilicon SoCs DT updates for 5.2

* Hi3660 SoC and related boards:
  - Added DMA support for the uart nodes
  - Added the asp DMA controller node
  - Replaced dma-min-chan with dma-channel-mask to follow the binding

* Hi3670 SoC and related boards:
  - Reused Hi3660 reset to support Hi3670, updated the binding
    document and added dts node
  - Reused Hi3660 MMC controller to support Hi3670, updated the
    binding document and added related nodes to support SD and WiFi
    for the SoC and hikey970 board
  - Added UFS controller node

* tag 'hisi-arm64-dt-for-5.2' of git://github.com/hisilicon/linux-hisi

:
  arm64: dts: hisilicon: hi3670: Add UFS controller support
  arm64: dts: hi3660: Fixup unofficial dma-min-chan to dma-channel-mask
  arm64: dts: hi3660: Add hisi asp dma device
  arm64: dts: hi3660: Add dma to uart nodes
  arm64: dts: hisilicon: hikey970: Add SD and WiFi support
  arm64: dts: hisilicon: hi3670: Add MMC controller support
  dt-bindings: mmc: Add HI3670 MMC controller binding
  arm64: dts: hisilicon: hi3670: Add reset controller support
  dt-bindings: reset: Add HI3670 reset controller binding

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 236a4234 ddd0dc91

Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt

+2 −0
Original line number Diff line number Diff line
@@ -13,6 +13,8 @@ Required Properties: 


* compatible: should be one of the following.

  - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.

  - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers

     with hi3670 specific extensions.

  - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.

  - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.

Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt

+4 −3
Original line number Diff line number Diff line
@@ -5,11 +5,12 @@ Please also refer to reset.txt in this directory for common reset 
controller binding usage.



The reset controller registers are part of the system-ctl block on

hi3660 SoC.

hi3660 and hi3670 SoCs.



Required properties:

- compatible: should be

		 "hisilicon,hi3660-reset"

- compatible: should be one of the following:

		 "hisilicon,hi3660-reset" for HI3660

		 "hisilicon,hi3670-reset", "hisilicon,hi3660-reset" for HI3670

- hisi,rst-syscon: phandle of the reset's syscon.

- #reset-cells : Specifies the number of cells needed to encode a

  reset source.  The type shall be a <u32> and the value shall be 2.

arch/arm64/boot/dts/hisilicon/hi3660.dtsi

+19 −1
Original line number Diff line number Diff line
@@ -478,6 +478,8 @@ 
			compatible = "arm,pl011", "arm,primecell";

			reg = <0x0 0xfdf00000 0x0 0x1000>;

			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;

			dma-names = "rx", "tx";

			dmas =  <&dma0 2 &dma0 3>;

			clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,

				 <&crg_ctrl HI3660_CLK_GATE_UART1>;

			clock-names = "uartclk", "apb_pclk";
@@ -490,6 +492,8 @@ 
			compatible = "arm,pl011", "arm,primecell";

			reg = <0x0 0xfdf03000 0x0 0x1000>;

			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;

			dma-names = "rx", "tx";

			dmas =  <&dma0 4 &dma0 5>;

			clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,

				 <&crg_ctrl HI3660_PCLK>;

			clock-names = "uartclk", "apb_pclk";
@@ -514,6 +518,8 @@ 
			compatible = "arm,pl011", "arm,primecell";

			reg = <0x0 0xfdf01000 0x0 0x1000>;

			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;

			dma-names = "rx", "tx";

			dmas =  <&dma0 6 &dma0 7>;

			clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,

				 <&crg_ctrl HI3660_CLK_GATE_UART4>;

			clock-names = "uartclk", "apb_pclk";
@@ -526,6 +532,8 @@ 
			compatible = "arm,pl011", "arm,primecell";

			reg = <0x0 0xfdf05000 0x0 0x1000>;

			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;

			dma-names = "rx", "tx";

			dmas =  <&dma0 8 &dma0 9>;

			clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,

				 <&crg_ctrl HI3660_CLK_GATE_UART5>;

			clock-names = "uartclk", "apb_pclk";
@@ -552,13 +560,23 @@ 
			#dma-cells = <1>;

			dma-channels = <16>;

			dma-requests = <32>;

			dma-min-chan = <1>;

			dma-channel-mask = <0xfffe>;

			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;

			dma-no-cci;

			dma-type = "hi3660_dma";

		};



		asp_dmac: dma-controller@e804b000 {

			compatible = "hisilicon,hisi-pcm-asp-dma-1.0";

			reg = <0x0 0xe804b000 0x0 0x1000>;

			#dma-cells = <1>;

			dma-channels = <16>;

			dma-requests = <32>;

			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "asp_dma_irq";

		};



		rtc0: rtc@fff04000 {

			compatible = "arm,pl031", "arm,primecell";

			reg = <0x0 0Xfff04000 0x0 0x1000>;

arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts

+75 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
 */



/dts-v1/;

#include <dt-bindings/gpio/gpio.h>



#include "hi3670.dtsi"

#include "hikey970-pinctrl.dtsi"
@@ -17,6 +18,8 @@ 
	compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";



	aliases {

		mshc1 = &dwmmc1;

		mshc2 = &dwmmc2;

		serial0 = &uart0;

		serial1 = &uart1;

		serial2 = &uart2;
@@ -35,6 +38,37 @@ 
		/* expect bootloader to fill in this region */

		reg = <0x0 0x0 0x0 0x0>;

	};



	sd_1v8: regulator-1v8 {

		compatible = "regulator-fixed";

		regulator-name = "fixed-1.8V";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <1800000>;

		regulator-always-on;

	};



	sd_3v3: regulator-3v3 {

		compatible = "regulator-fixed";

		regulator-name = "fixed-3.3V";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		regulator-boot-on;

		regulator-always-on;

	};



	wlan_en: wlan-en-1-8v {

		compatible = "regulator-fixed";

		regulator-name = "wlan-en-regulator";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <1800000>;



		/* GPIO_051_WIFI_EN */

		gpio = <&gpio6 3 0>;



		/* WLAN card specific delay */

		startup-delay-us = <70000>;

		enable-active-high;

	};

};



/*
@@ -354,6 +388,47 @@ 
		"GPIO_231_HDMI_INT";

};



&dwmmc1 {

	bus-width = <0x4>;

	sd-uhs-sdr12;

	sd-uhs-sdr25;

	sd-uhs-sdr50;

	sd-uhs-sdr104;

	cap-sd-highspeed;

	disable-wp;

	cd-inverted;

	cd-gpios = <&gpio25 5 GPIO_ACTIVE_HIGH>;

	pinctrl-names = "default";

	pinctrl-0 = <&sd_pmx_func

		     &sd_clk_cfg_func

		     &sd_cfg_func>;

	vmmc-supply = <&sd_3v3>;

	vqmmc-supply = <&sd_1v8>;

	status = "okay";

};



&dwmmc2 { /* WIFI */

	bus-width = <0x4>;

	non-removable;

	broken-cd;

	cap-power-off-card;

	pinctrl-names = "default";

	pinctrl-0 = <&sdio_pmx_func

		     &sdio_clk_cfg_func

		     &sdio_cfg_func>;

	/* WL_EN */

	vmmc-supply = <&wlan_en>;

	status = "ok";



	wlcore: wlcore@2 {

		compatible = "ti,wl1837";

		reg = <2>;      /* sdio func num */

		/* WL_IRQ, GPIO_177_WL_WAKEUP_AP */

		interrupt-parent = <&gpio22>;

		interrupts = <1 IRQ_TYPE_EDGE_RISING>;

	};

};



&uart0 {

	/* On High speed expansion header */

	label = "HS-UART0";

arch/arm64/boot/dts/hisilicon/hi3670.dtsi

+62 −0
Original line number Diff line number Diff line
@@ -151,6 +151,13 @@ 
			#clock-cells = <1>;

		};



		crg_rst: crg_rst_controller {

			compatible = "hisilicon,hi3670-reset",

				     "hisilicon,hi3660-reset";

			#reset-cells = <2>;

			hisi,rst-syscon = <&crg_ctrl>;

		};



		pctrl: pctrl@e8a09000 {

			compatible = "hisilicon,hi3670-pctrl", "syscon";

			reg = <0x0 0xe8a09000 0x0 0x1000>;
@@ -647,5 +654,60 @@ 
			clocks = <&sctrl HI3670_PCLK_AO_GPIO6>;

			clock-names = "apb_pclk";

		};



		/* UFS */

		ufs: ufs@ff3c0000 {

			compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";

			/* 0: HCI standard */

			/* 1: UFS SYS CTRL */

			reg = <0x0 0xff3c0000 0x0 0x1000>,

				<0x0 0xff3e0000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,

				<&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;

			clock-names = "ref_clk", "phy_clk";

			freq-table-hz = <0 0>, <0 0>;

			/* offset: 0x84; bit: 12 */

			resets = <&crg_rst 0x84 12>;

			reset-names = "rst";

		};



		/* SD */

		dwmmc1: dwmmc1@ff37f000 {

			compatible = "hisilicon,hi3670-dw-mshc",

				     "hisilicon,hi3660-dw-mshc";

			reg = <0x0 0xff37f000 0x0 0x1000>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg_ctrl HI3670_CLK_GATE_SD>,

				<&crg_ctrl HI3670_HCLK_GATE_SD>;

			clock-names = "ciu", "biu";

			clock-frequency = <3200000>;

			resets = <&crg_rst 0x94 18>;

			reset-names = "reset";

			hisilicon,peripheral-syscon = <&sctrl>;

			card-detect-delay = <200>;

			status = "disabled";

		};



		/* SDIO */

		dwmmc2: dwmmc2@fc183000 {

			compatible = "hisilicon,hi3670-dw-mshc",

				     "hisilicon,hi3660-dw-mshc";

			reg = <0x0 0xfc183000 0x0 0x1000>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg_ctrl HI3670_CLK_GATE_SDIO>,

				<&crg_ctrl HI3670_HCLK_GATE_SDIO>;

			clock-names = "ciu", "biu";

			clock-frequency = <3200000>;

			resets = <&crg_rst 0x94 20>;

			reset-names = "reset";

			card-detect-delay = <200>;

			status = "disabled";

		};

	};

};

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