Commit 1b790cd9 authored by Oscar Mateo's avatar Oscar Mateo Committed by Chris Wilson
Browse files

drm/i915: Remove Gen9 WAs with no effect 



GEN8_CONFIG0 (0xD00) is a protected by a lock (bit 31) which is set by
the BIOS, so there is no way we can enable the three chicken bits
mandated by the WA (the BIOS should be doing it instead).

v2: Rebased
v3: Standalone patch

References: b033bb6d ("drm/i915/gen9: Enable must set chicken bits in config0 reg")
Signed-off-by: default avatarOscar Mateo <oscar.mateo@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1510185589-9100-2-git-send-email-oscar.mateo@intel.com


Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 37cd3300

drivers/gpu/drm/i915/i915_reg.h

+0 −3
Original line number Diff line number Diff line
@@ -355,9 +355,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define   ECOCHK_PPGTT_WT_HSW		(0x2<<3)

#define   ECOCHK_PPGTT_WB_HSW		(0x3<<3)



#define GEN8_CONFIG0			_MMIO(0xD00)

#define  GEN9_DEFAULT_FIXES		(1 << 3 | 1 << 2 | 1 << 1)



#define GAC_ECO_BITS			_MMIO(0x14090)

#define   ECOBITS_SNB_BIT		(1<<13)

#define   ECOBITS_PPGTT_CACHE64B	(3<<8)

drivers/gpu/drm/i915/intel_pm.c

+0 −3
Original line number Diff line number Diff line
@@ -75,9 +75,6 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) 
	I915_WRITE(CHICKEN_PAR1_1,

		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);



	I915_WRITE(GEN8_CONFIG0,

		   I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);



	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */

	I915_WRITE(GEN8_CHICKEN_DCPR_1,

		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);

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