Commit b033bb6d authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Mika Kuoppala
Browse files

drm/i915/gen9: Enable must set chicken bits in config0 reg 



The bspec states that these must be set in CONFIG0 for all gen9.

v2: rebase
v3: fix spacing (Matthew)

References: HSD#2134995
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-13-git-send-email-mika.kuoppala@intel.com
parent fe905819

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -220,6 +220,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define   ECOCHK_PPGTT_WT_HSW		(0x2<<3)

#define   ECOCHK_PPGTT_WB_HSW		(0x3<<3)



#define GEN8_CONFIG0			_MMIO(0xD00)

#define  GEN9_DEFAULT_FIXES		(1 << 3 | 1 << 2 | 1 << 1)



#define GAC_ECO_BITS			_MMIO(0x14090)

#define   ECOBITS_SNB_BIT		(1<<13)

#define   ECOBITS_PPGTT_CACHE64B	(3<<8)

drivers/gpu/drm/i915/intel_pm.c

+14 −10
Original line number Diff line number Diff line
@@ -55,14 +55,24 @@ 
#define INTEL_RC6p_ENABLE			(1<<1)

#define INTEL_RC6pp_ENABLE			(1<<2)



static void bxt_init_clock_gating(struct drm_device *dev)

static void gen9_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	/* See Bspec note for PSR2_CTL bit 31, Wa#828:bxt */

	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */

	I915_WRITE(CHICKEN_PAR1_1,

		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);



	I915_WRITE(GEN8_CONFIG0,

		   I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);

}



static void bxt_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	gen9_init_clock_gating(dev);



	/* WaDisableSDEUnitClockGating:bxt */

	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |

		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
@@ -6967,9 +6977,7 @@ static void kabylake_init_clock_gating(struct drm_device *dev) 
{

	struct drm_i915_private *dev_priv = dev->dev_private;



	/* See Bspec note for PSR2_CTL bit 31, Wa#828:kbl */

	I915_WRITE(CHICKEN_PAR1_1,

		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);

	gen9_init_clock_gating(dev);



	/* WaDisableSDEUnitClockGating:kbl */

	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
@@ -6979,11 +6987,7 @@ static void kabylake_init_clock_gating(struct drm_device *dev) 


static void skylake_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl */

	I915_WRITE(CHICKEN_PAR1_1,

		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);

	gen9_init_clock_gating(dev);

}



static void broadwell_init_clock_gating(struct drm_device *dev)

CRA Git | Maintained and supported by SUSTech CRA and CCSE