Commit 195f1403 authored by Guillaume La Roque's avatar Guillaume La Roque Committed by Kevin Hilman
Browse files

arm64: dts: meson: g12b: add cooling properties 



Add missing #colling-cells field for G12B SoC
Add cooling-map for passive and hot trip point

Tested-by: default avatarChristian Hewitt <christianshewitt@gmail.com>
Tested-by: default avatarKevin Hilman <khilman@baylibre.com>
Reviewed-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: default avatarAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: default avatarGuillaume La Roque <glaroque@baylibre.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent 8eef8bca

arch/arm64/boot/dts/amlogic/meson-g12.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -347,6 +347,29 @@ 
	};

};



&cpu_thermal {

	cooling-maps {

		map0 {

			trip = <&cpu_passive>;

			cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

					 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

					 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

					 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

					 <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

					 <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

		};

		map1 {

			trip = <&cpu_hot>;

			cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

					 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

					 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

					 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

					 <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

					 <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

		};

	};

};



&ethmac {

	power-domains = <&pwrc PWRC_G12A_ETH_ID>;

};
@@ -366,3 +389,4 @@ 
&simplefb_hdmi {

	power-domains = <&pwrc PWRC_G12A_VPU_ID>;

};

arch/arm64/boot/dts/amlogic/meson-g12b.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <592>;

			next-level-cache = <&l2>;

			#cooling-cells = <2>;

		};



		cpu1: cpu@1 {
@@ -59,6 +60,7 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <592>;

			next-level-cache = <&l2>;

			#cooling-cells = <2>;

		};



		cpu100: cpu@100 {
@@ -68,6 +70,7 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			next-level-cache = <&l2>;

			#cooling-cells = <2>;

		};



		cpu101: cpu@101 {
@@ -77,6 +80,7 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			next-level-cache = <&l2>;

			#cooling-cells = <2>;

		};



		cpu102: cpu@102 {
@@ -86,6 +90,7 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			next-level-cache = <&l2>;

			#cooling-cells = <2>;

		};



		cpu103: cpu@103 {
@@ -95,6 +100,7 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			next-level-cache = <&l2>;

			#cooling-cells = <2>;

		};



		l2: l2-cache0 {

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