Commit 8eef8bca authored by Guillaume La Roque's avatar Guillaume La Roque Committed by Kevin Hilman
Browse files

arm64: dts: meson: g12a: add cooling properties 



Add missing #colling-cells field for G12A SoC
Add cooling-map for passive and hot trip point

Tested-by: default avatarChristian Hewitt <christianshewitt@gmail.com>
Tested-by: default avatarKevin Hilman <khilman@baylibre.com>
Reviewed-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: default avatarAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: default avatarGuillaume La Roque <glaroque@baylibre.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent e7251ed7

arch/arm64/boot/dts/amlogic/meson-g12a.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
			reg = <0x0 0x0>;

			enable-method = "psci";

			next-level-cache = <&l2>;

			#cooling-cells = <2>;

		};



		cpu1: cpu@1 {
@@ -26,6 +27,7 @@ 
			reg = <0x0 0x1>;

			enable-method = "psci";

			next-level-cache = <&l2>;

			#cooling-cells = <2>;

		};



		cpu2: cpu@2 {
@@ -34,6 +36,7 @@ 
			reg = <0x0 0x2>;

			enable-method = "psci";

			next-level-cache = <&l2>;

			#cooling-cells = <2>;

		};



		cpu3: cpu@3 {
@@ -42,6 +45,7 @@ 
			reg = <0x0 0x3>;

			enable-method = "psci";

			next-level-cache = <&l2>;

			#cooling-cells = <2>;

		};



		l2: l2-cache0 {
@@ -109,3 +113,23 @@ 
		};

	};

};



&cpu_thermal {

	cooling-maps {

		map0 {

			trip = <&cpu_passive>;

			cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

					<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

					<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

					<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

		};



		map1 {

			trip = <&cpu_hot>;

			cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

					<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

					<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

					<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

		};

	};

};

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