drm/amdgpu: disable 3D pipe 1 on Navi1x (194bcf35) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+51 −46

Original line number	Original line	Diff line number	Diff line
	@@ -52,7 +52,7 @@
	* 1. Primary ring		* 1. Primary ring
	* 2. Async ring		* 2. Async ring
	*/		*/
	#define GFX10_NUM_GFX_RINGS 2		#define GFX10_NUM_GFX_RINGS_NV1X 1
	#define GFX10_MEC_HPD_SIZE 2048		#define GFX10_MEC_HPD_SIZE 2048

	#define F32_CE_PROGRAM_RAM_SIZE 65536		#define F32_CE_PROGRAM_RAM_SIZE 65536
	@@ -1304,7 +1304,7 @@ static int gfx_v10_0_sw_init(void *handle)
	case CHIP_NAVI14:		case CHIP_NAVI14:
	case CHIP_NAVI12:		case CHIP_NAVI12:
	adev->gfx.me.num_me = 1;		adev->gfx.me.num_me = 1;
	adev->gfx.me.num_pipe_per_me = 2;		adev->gfx.me.num_pipe_per_me = 1;
	adev->gfx.me.num_queue_per_pipe = 1;		adev->gfx.me.num_queue_per_pipe = 1;
	adev->gfx.mec.num_mec = 2;		adev->gfx.mec.num_mec = 2;
	adev->gfx.mec.num_pipe_per_mec = 4;		adev->gfx.mec.num_pipe_per_mec = 4;
	@@ -2710,6 +2710,8 @@ static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
	amdgpu_ring_commit(ring);		amdgpu_ring_commit(ring);

	/* submit cs packet to copy state 0 to next available state */		/* submit cs packet to copy state 0 to next available state */
			if (adev->gfx.num_gfx_rings > 1) {
			/* maximum supported gfx ring is 2 */
	ring = &adev->gfx.gfx_ring[1];		ring = &adev->gfx.gfx_ring[1];
	r = amdgpu_ring_alloc(ring, 2);		r = amdgpu_ring_alloc(ring, 2);
	if (r) {		if (r) {
	@@ -2721,7 +2723,7 @@ static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
	amdgpu_ring_write(ring, 0);		amdgpu_ring_write(ring, 0);

	amdgpu_ring_commit(ring);		amdgpu_ring_commit(ring);
			}
	return 0;		return 0;
	}		}

	@@ -2818,8 +2820,10 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
	mutex_unlock(&adev->srbm_mutex);		mutex_unlock(&adev->srbm_mutex);

	/* Init gfx ring 1 for pipe 1 */		/* Init gfx ring 1 for pipe 1 */
			if (adev->gfx.num_gfx_rings > 1) {
	mutex_lock(&adev->srbm_mutex);		mutex_lock(&adev->srbm_mutex);
	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);		gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
			/* maximum supported gfx ring is 2 */
	ring = &adev->gfx.gfx_ring[1];		ring = &adev->gfx.gfx_ring[1];
	rb_bufsz = order_base_2(ring->ring_size / 8);		rb_bufsz = order_base_2(ring->ring_size / 8);
	tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);		tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
	@@ -2850,7 +2854,7 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)

	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);		gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
	mutex_unlock(&adev->srbm_mutex);		mutex_unlock(&adev->srbm_mutex);
			}
	/* Switch to pipe 0 */		/* Switch to pipe 0 */
	mutex_lock(&adev->srbm_mutex);		mutex_lock(&adev->srbm_mutex);
	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);		gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
	@@ -3967,7 +3971,8 @@ static int gfx_v10_0_early_init(void *handle)
	{		{
	struct amdgpu_device adev = (struct amdgpu_device )handle;		struct amdgpu_device adev = (struct amdgpu_device )handle;

	adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS;		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;

	adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;		adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;

	gfx_v10_0_set_kiq_pm4_funcs(adev);		gfx_v10_0_set_kiq_pm4_funcs(adev);

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