Commit 18aa3bd5 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge branch 'for-next/tlbi' into for-next/core 

* for-next/tlbi:
  : Support for TTL (translation table level) hint in the TLB operations
  arm64: tlb: Use the TLBI RANGE feature in arm64
  arm64: enable tlbi range instructions
  arm64: tlb: Detect the ARMv8.4 TLBI RANGE feature
  arm64: tlb: don't set the ttl value in flush_tlb_page_nosync
  arm64: Shift the __tlbi_level() indentation left
  arm64: tlb: Set the TTL field in flush_*_tlb_range
  arm64: tlb: Set the TTL field in flush_tlb_range
  tlb: mmu_gather: add tlb_flush_*_range APIs
  arm64: Add tlbi_user_level TLB invalidation helper
  arm64: Add level-hinted TLB invalidation helper
  arm64: Document SW reserved PTE/PMD bits in Stage-2 descriptors
  arm64: Detect the ARMv8.4 TTL feature
parents 4557062d d1d3aa98

arch/arm64/Kconfig

+14 −0
Original line number Diff line number Diff line
@@ -1601,6 +1601,20 @@ config ARM64_AMU_EXTN 
	  correctly reflect reality. Most commonly, the value read will be 0,

	  indicating that the counter is not enabled.



config AS_HAS_ARMV8_4

	def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)



config ARM64_TLB_RANGE

	bool "Enable support for tlbi range feature"

	default y

	depends on AS_HAS_ARMV8_4

	help

	  ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a

	  range of input addresses.



	  The feature introduces new assembly instructions, and they were

	  support when binutils >= 2.30.



endmenu



menu "ARMv8.5 architectural features"

arch/arm64/Makefile

+7 −0
Original line number Diff line number Diff line
@@ -82,11 +82,18 @@ endif 
# compiler to generate them and consequently to break the single image contract

# we pass it only to the assembler. This option is utilized only in case of non

# integrated assemblers.

ifneq ($(CONFIG_AS_HAS_ARMV8_4), y)

branch-prot-flags-$(CONFIG_AS_HAS_PAC) += -Wa,-march=armv8.3-a

endif

endif



KBUILD_CFLAGS += $(branch-prot-flags-y)



ifeq ($(CONFIG_AS_HAS_ARMV8_4), y)

# make sure to pass the newest target architecture to -march.

KBUILD_CFLAGS	+= -Wa,-march=armv8.4-a

endif



ifeq ($(CONFIG_SHADOW_CALL_STACK), y)

KBUILD_CFLAGS	+= -ffixed-x18

endif

arch/arm64/include/asm/cpucaps.h

+3 −1
Original line number Diff line number Diff line
@@ -62,7 +62,9 @@ 
#define ARM64_HAS_GENERIC_AUTH			52

#define ARM64_HAS_32BIT_EL1			53

#define ARM64_BTI				54

#define ARM64_HAS_ARMv8_4_TTL			55

#define ARM64_HAS_TLB_RANGE			56



#define ARM64_NCAPS				55

#define ARM64_NCAPS				57



#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/cpufeature.h

+6 −0
Original line number Diff line number Diff line
@@ -692,6 +692,12 @@ static inline bool system_supports_bti(void) 
	return IS_ENABLED(CONFIG_ARM64_BTI) && cpus_have_const_cap(ARM64_BTI);

}



static inline bool system_supports_tlb_range(void)

{

	return IS_ENABLED(CONFIG_ARM64_TLB_RANGE) &&

		cpus_have_const_cap(ARM64_HAS_TLB_RANGE);

}



#define ARM64_BP_HARDEN_UNKNOWN		-1

#define ARM64_BP_HARDEN_WA_NEEDED	0

#define ARM64_BP_HARDEN_NOT_REQUIRED	1

arch/arm64/include/asm/pgtable-hwdef.h

+2 −0
Original line number Diff line number Diff line
@@ -178,10 +178,12 @@ 
#define PTE_S2_RDONLY		(_AT(pteval_t, 1) << 6)   /* HAP[2:1] */

#define PTE_S2_RDWR		(_AT(pteval_t, 3) << 6)   /* HAP[2:1] */

#define PTE_S2_XN		(_AT(pteval_t, 2) << 53)  /* XN[1:0] */

#define PTE_S2_SW_RESVD		(_AT(pteval_t, 15) << 55) /* Reserved for SW */



#define PMD_S2_RDONLY		(_AT(pmdval_t, 1) << 6)   /* HAP[2:1] */

#define PMD_S2_RDWR		(_AT(pmdval_t, 3) << 6)   /* HAP[2:1] */

#define PMD_S2_XN		(_AT(pmdval_t, 2) << 53)  /* XN[1:0] */

#define PMD_S2_SW_RESVD		(_AT(pmdval_t, 15) << 55) /* Reserved for SW */



#define PUD_S2_RDONLY		(_AT(pudval_t, 1) << 6)   /* HAP[2:1] */

#define PUD_S2_RDWR		(_AT(pudval_t, 3) << 6)   /* HAP[2:1] */

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