Commit 4557062d authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge branches 'for-next/misc', 'for-next/vmcoreinfo', 'for-next/cpufeature',... 

Merge branches 'for-next/misc', 'for-next/vmcoreinfo', 'for-next/cpufeature', 'for-next/acpi', 'for-next/perf', 'for-next/timens', 'for-next/msi-iommu' and 'for-next/trivial' into for-next/core

* for-next/misc:
  : Miscellaneous fixes and cleanups
  arm64: use IRQ_STACK_SIZE instead of THREAD_SIZE for irq stack
  arm64/mm: save memory access in check_and_switch_context() fast switch path
  recordmcount: only record relocation of type R_AARCH64_CALL26 on arm64.
  arm64: Reserve HWCAP2_MTE as (1 << 18)
  arm64/entry: deduplicate SW PAN entry/exit routines
  arm64: s/AMEVTYPE/AMEVTYPER
  arm64/hugetlb: Reserve CMA areas for gigantic pages on 16K and 64K configs
  arm64: stacktrace: Move export for save_stack_trace_tsk()
  smccc: Make constants available to assembly
  arm64/mm: Redefine CONT_{PTE, PMD}_SHIFT
  arm64/defconfig: Enable CONFIG_KEXEC_FILE
  arm64: Document sysctls for emulated deprecated instructions
  arm64/panic: Unify all three existing notifier blocks
  arm64/module: Optimize module load time by optimizing PLT counting

* for-next/vmcoreinfo:
  : Export the virtual and physical address sizes in vmcoreinfo
  arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo
  crash_core, vmcoreinfo: Append 'MAX_PHYSMEM_BITS' to vmcoreinfo

* for-next/cpufeature:
  : CPU feature handling cleanups
  arm64/cpufeature: Validate feature bits spacing in arm64_ftr_regs[]
  arm64/cpufeature: Replace all open bits shift encodings with macros
  arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 register
  arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register
  arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register

* for-next/acpi:
  : ACPI updates for arm64
  arm64/acpi: disallow writeable AML opregion mapping for EFI code regions
  arm64/acpi: disallow AML memory opregions to access kernel memory

* for-next/perf:
  : perf updates for arm64
  arm64: perf: Expose some new events via sysfs
  tools headers UAPI: Update tools's copy of linux/perf_event.h
  arm64: perf: Add cap_user_time_short
  perf: Add perf_event_mmap_page::cap_user_time_short ABI
  arm64: perf: Only advertise cap_user_time for arch_timer
  arm64: perf: Implement correct cap_user_time
  time/sched_clock: Use raw_read_seqcount_latch()
  sched_clock: Expose struct clock_read_data
  arm64: perf: Correct the event index in sysfs
  perf/smmuv3: To simplify code for ioremap page in pmcg

* for-next/timens:
  : Time namespace support for arm64
  arm64: enable time namespace support
  arm64/vdso: Restrict splitting VVAR VMA
  arm64/vdso: Handle faults on timens page
  arm64/vdso: Add time namespace page
  arm64/vdso: Zap vvar pages when switching to a time namespace
  arm64/vdso: use the fault callback to map vvar pages

* for-next/msi-iommu:
  : Make the MSI/IOMMU input/output ID translation PCI agnostic, augment the
  : MSI/IOMMU ACPI/OF ID mapping APIs to accept an input ID bus-specific parameter
  : and apply the resulting changes to the device ID space provided by the
  : Freescale FSL bus
  bus: fsl-mc: Add ACPI support for fsl-mc
  bus/fsl-mc: Refactor the MSI domain creation in the DPRC driver
  of/irq: Make of_msi_map_rid() PCI bus agnostic
  of/irq: make of_msi_map_get_device_domain() bus agnostic
  dt-bindings: arm: fsl: Add msi-map device-tree binding for fsl-mc bus
  of/device: Add input id to of_dma_configure()
  of/iommu: Make of_map_rid() PCI agnostic
  ACPI/IORT: Add an input ID to acpi_dma_configure()
  ACPI/IORT: Remove useless PCI bus walk
  ACPI/IORT: Make iort_msi_map_rid() PCI agnostic
  ACPI/IORT: Make iort_get_device_domain IRQ domain agnostic
  ACPI/IORT: Make iort_match_node_callback walk the ACPI namespace for NC

* for-next/trivial:
  : Trivial fixes
  arm64: sigcontext.h: delete duplicated word
  arm64: ptrace.h: delete duplicated word
  arm64: pgtable-hwdef.h: delete duplicated words
parents 338c11e9 bbdbc118 c6c83d75 325f5585 55fdc1f4 9614cc57 6305166c 1a9ea25d

Documentation/admin-guide/kdump/vmcoreinfo.rst

+16 −0
Original line number Diff line number Diff line
@@ -93,6 +93,11 @@ It exists in the sparse memory mapping model, and it is also somewhat 
similar to the mem_map variable, both of them are used to translate an

address.



MAX_PHYSMEM_BITS

----------------



Defines the maximum supported physical address space memory.



page

----
@@ -399,6 +404,17 @@ KERNELPACMASK 
The mask to extract the Pointer Authentication Code from a kernel virtual

address.



TCR_EL1.T1SZ

------------



Indicates the size offset of the memory region addressed by TTBR1_EL1.

The region size is 2^(64-T1SZ) bytes.



TTBR1_EL1 is the table base address register specified by ARMv8-A

architecture which is used to lookup the page-tables for the Virtual

addresses in the higher VA range (refer to ARMv8 ARM document for

more details).



arm

===

Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt

+44 −6
Original line number Diff line number Diff line
@@ -28,6 +28,16 @@ Documentation/devicetree/bindings/iommu/iommu.txt. 
For arm-smmu binding, see:

Documentation/devicetree/bindings/iommu/arm,smmu.yaml.



The MSI writes are accompanied by sideband data which is derived from the ICID.

The msi-map property is used to associate the devices with both the ITS

controller and the sideband data which accompanies the writes.



For generic MSI bindings, see

Documentation/devicetree/bindings/interrupt-controller/msi.txt.



For GICv3 and GIC ITS bindings, see:

Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml.



Required properties:



    - compatible
@@ -49,11 +59,6 @@ Required properties: 
                        region may not be present in some scenarios, such

                        as in the device tree presented to a virtual machine.



    - msi-parent

        Value type: <phandle>

        Definition: Must be present and point to the MSI controller node

                    handling message interrupts for the MC.



    - ranges

        Value type: <prop-encoded-array>

        Definition: A standard property.  Defines the mapping between the child
@@ -119,6 +124,28 @@ Optional properties: 
  associated with the listed IOMMU, with the iommu-specifier

  (i - icid-base + iommu-base).



- msi-map: Maps an ICID to a GIC ITS and associated msi-specifier

  data.



  The property is an arbitrary number of tuples of

  (icid-base,gic-its,msi-base,length).



  Any ICID in the interval [icid-base, icid-base + length) is

  associated with the listed GIC ITS, with the msi-specifier

  (i - icid-base + msi-base).



Deprecated properties:



    - msi-parent

        Value type: <phandle>

        Definition: Describes the MSI controller node handling message

                    interrupts for the MC. When there is no translation

                    between the ICID and deviceID this property can be used

                    to describe the MSI controller used by the devices on the

                    mc-bus.

                    The use of this property for mc-bus is deprecated. Please

                    use msi-map.



Example:



        smmu: iommu@5000000 {
@@ -128,13 +155,24 @@ Example: 
               ...

        };



        gic: interrupt-controller@6000000 {

               compatible = "arm,gic-v3";

               ...

        }

        its: gic-its@6020000 {

               compatible = "arm,gic-v3-its";

               msi-controller;

               ...

        };



        fsl_mc: fsl-mc@80c000000 {

                compatible = "fsl,qoriq-mc";

                reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */

                      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */

                msi-parent = <&its>;

                /* define map for ICIDs 23-64 */

                iommu-map = <23 &smmu 23 41>;

                /* define msi map for ICIDs 23-64 */

                msi-map = <23 &its 23 41>;

                #address-cells = <3>;

                #size-cells = <1>;

arch/arm64/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -118,6 +118,7 @@ config ARM64 
	select GENERIC_STRNLEN_USER

	select GENERIC_TIME_VSYSCALL

	select GENERIC_GETTIMEOFDAY

	select GENERIC_VDSO_TIME_NS

	select HANDLE_DOMAIN_IRQ

	select HARDIRQS_SW_RESEND

	select HAVE_PCI

arch/arm64/include/asm/acpi.h

+1 −14
Original line number Diff line number Diff line
@@ -47,20 +47,7 @@ 
pgprot_t __acpi_get_mem_attribute(phys_addr_t addr);



/* ACPI table mapping after acpi_permanent_mmap is set */

static inline void __iomem *acpi_os_ioremap(acpi_physical_address phys,

					    acpi_size size)

{

	/* For normal memory we already have a cacheable mapping. */

	if (memblock_is_map_memory(phys))

		return (void __iomem *)__phys_to_virt(phys);



	/*

	 * We should still honor the memory's attribute here because

	 * crash dump kernel possibly excludes some ACPI (reclaim)

	 * regions from memblock list.

	 */

	return __ioremap(phys, size, __acpi_get_mem_attribute(phys));

}

void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size);

#define acpi_os_ioremap acpi_os_ioremap



typedef u64 phys_cpuid_t;

arch/arm64/include/asm/perf_event.h

+27 −0
Original line number Diff line number Diff line
@@ -72,6 +72,13 @@ 
#define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD				0x36

#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD			0x37

#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD			0x38

#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD			0x39

#define ARMV8_PMUV3_PERFCTR_OP_RETIRED				0x3A

#define ARMV8_PMUV3_PERFCTR_OP_SPEC				0x3B

#define ARMV8_PMUV3_PERFCTR_STALL				0x3C

#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND			0x3D

#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND			0x3E

#define ARMV8_PMUV3_PERFCTR_STALL_SLOT				0x3F



/* Statistical profiling extension microarchitectural events */

#define	ARMV8_SPE_PERFCTR_SAMPLE_POP				0x4000
@@ -79,6 +86,26 @@ 
#define	ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE			0x4002

#define	ARMV8_SPE_PERFCTR_SAMPLE_COLLISION			0x4003



/* AMUv1 architecture events */

#define	ARMV8_AMU_PERFCTR_CNT_CYCLES				0x4004

#define	ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM			0x4005



/* long-latency read miss events */

#define	ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS			0x4006

#define	ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD			0x4009

#define	ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS			0x400A

#define	ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD			0x400B



/* additional latency from alignment events */

#define	ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT			0x4020

#define	ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT			0x4021

#define	ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT			0x4022



/* Armv8.5 Memory Tagging Extension events */

#define	ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED			0x4024

#define	ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD			0x4025

#define	ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR			0x4026



/* ARMv8 recommended implementation defined event types */

#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD			0x40

#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR			0x41

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