Commit 187f91db authored by Saheed O. Bolarinwa's avatar Saheed O. Bolarinwa Committed by Bjorn Helgaas
Browse files

PCI/ASPM: Remove struct aspm_register_info.l1ss_cap 

Previously we stored the L1SS Capabilities value in the struct
aspm_register_info.

We only need this information in one place, so read it there and remove
struct aspm_register_info completely, since it's now empty.  No functional
change intended.

[bhelgaas: split up, don't cache l1ss_cap in pci_dev]
Link: https://lore.kernel.org/r/20201015193039.12585-12-helgaas@kernel.org


Signed-off-by: default avatarSaheed O. Bolarinwa <refactormyself@gmail.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 1e8955fd

drivers/pci/pcie/aspm.c

+21 −32
Original line number Diff line number Diff line
@@ -382,26 +382,6 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) 
	}

}



struct aspm_register_info {

	/* L1 substates */

	u32 l1ss_cap;

};



static void pcie_get_aspm_reg(struct pci_dev *pdev,

			      struct aspm_register_info *info)

{

	/* Read L1 PM substate capabilities */

	info->l1ss_cap = 0;



	if (!pdev->l1ss)

		return;



	pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CAP,

			      &info->l1ss_cap);

	if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))

		info->l1ss_cap = 0;

}



static void pcie_aspm_check_latency(struct pci_dev *endpoint)

{

	u32 latency, l1_switch_latency = 0;
@@ -527,9 +507,9 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) 
	struct pci_dev *child = link->downstream, *parent = link->pdev;

	u32 parent_lnkcap, child_lnkcap;

	u16 parent_lnkctl, child_lnkctl;

	u32 parent_l1ss_cap, child_l1ss_cap;

	u32 parent_l1ss_ctl1 = 0, child_l1ss_ctl1 = 0;

	struct pci_bus *linkbus = parent->subordinate;

	struct aspm_register_info upreg, dwreg;



	if (blacklist) {

		/* Set enabled/disable so that we will disable ASPM later */
@@ -560,8 +540,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) 
	pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);

	pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);

	pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);

	pcie_get_aspm_reg(parent, &upreg);

	pcie_get_aspm_reg(child, &dwreg);



	/*

	 * Setup L0s state
@@ -589,27 +567,38 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) 
	link->latency_up.l1 = calc_l1_latency(parent_lnkcap);

	link->latency_dw.l1 = calc_l1_latency(child_lnkcap);



	/* Setup L1 substate

	/* Setup L1 substate */

	pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,

			      &parent_l1ss_cap);

	pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP,

			      &child_l1ss_cap);



	if (!(parent_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))

		parent_l1ss_cap = 0;

	if (!(child_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))

		child_l1ss_cap = 0;



	/*

	 * If we don't have LTR for the entire path from the Root Complex

	 * to this device, we can't use ASPM L1.2 because it relies on the

	 * LTR_L1.2_THRESHOLD.  See PCIe r4.0, secs 5.5.4, 6.18.

	 */

	if (!child->ltr_path)

		dwreg.l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;

		child_l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;



	if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)

	if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)

		link->aspm_support |= ASPM_STATE_L1_1;

	if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)

	if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)

		link->aspm_support |= ASPM_STATE_L1_2;

	if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)

	if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)

		link->aspm_support |= ASPM_STATE_L1_1_PCIPM;

	if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)

	if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)

		link->aspm_support |= ASPM_STATE_L1_2_PCIPM;



	if (upreg.l1ss_cap)

	if (parent_l1ss_cap)

		pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,

				      &parent_l1ss_ctl1);

	if (dwreg.l1ss_cap)

	if (child_l1ss_cap)

		pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1,

				      &child_l1ss_ctl1);
@@ -623,7 +612,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) 
		link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;



	if (link->aspm_support & ASPM_STATE_L1SS)

		aspm_calc_l1ss_info(link, upreg.l1ss_cap, dwreg.l1ss_cap);

		aspm_calc_l1ss_info(link, parent_l1ss_cap, child_l1ss_cap);



	/* Save default state */

	link->aspm_default = link->aspm_enabled;

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