Commit 1749e1fc authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'sti-dt-for-v3.19-1' of git://git.stlinux.com/devel/kernel/linux-sti into next/dt 

Merge "STi DT updates for v3.19, round 1" from Maxime Coquelin:

Highlights:
-----------
 - Add SDHCI support for STiH41x B2020 boards
 - Add reset controllers to STiH407 SoC
 - Add MiPHY & SATA support to STiH416
 - Add Thermal supportto STiH416
 - Add Clock support to STiH407 SoC

This tag also includes STiH407 bindings definitions for reset controller.

* tag 'sti-dt-for-v3.19-1' of git://git.stlinux.com/devel/kernel/linux-sti

:
  ARM: STi: DT: STiH407: Fix: clk-tmds-hdmi clock is missing
  ARM: STi: DT: STiH407: Add all defines for STiH407 DT clocks
  ARM: STi: DT: STiH407: 407 DT Entry for clockgenA9
  ARM: STi: DT: STiH407: 407 DT Entry for clockgen D0/D2/D3
  ARM: STi: DT: STiH407: 407 DT Entry for clockgen C0
  ARM: STi: DT: STiH407: 407 DT Entry for clockgen A0
  ARM: DT: STi: STiH416: Add DT node for ST's SATA device
  ARM: DT: STi: STiH416: Add DT node for MiPHY365x
  ARM: STi: DT: STiH416: Supply Thermal Controller Device Tree nodes
  ARM: STi: DT: Enable second sdhci controller for stih416 b2020 boards.
  ARM: STi: DT: Enable mmc0 for both stih415 and stih416 SoCs
  ARM: STi: DT: Add sdhci controller for stih415
  ARM: STi: DT: Add sdhci pin configuration for stih415
  ARM: STi: DT: Add sdhci controller for stih416
  ARM: STi: DT: Add sdhci pins for stih416
  ARM: sti: Add STiH407 reset controller support.
  ARM: sti: Add STiH407 Kconfig entry to select STIH407_RESET
  ARM: STi: DT: STiH41x: Convert all uppercase non-defines to lowercase
  reset: stih407: Add reset controllers DT bindings

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 1ba5568c 43ca480c

arch/arm/boot/dts/stih407-clock.dtsi

+290 −3
Original line number Diff line number Diff line
@@ -5,8 +5,13 @@ 
 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

#include <dt-bindings/clock/stih407-clks.h>

/ {

	clocks {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		/*

		 * Fixed 30MHz oscillator inputs to SoC

		 */
@@ -19,10 +24,59 @@ 
		/*

		 * ARM Peripheral clock for timers

		 */

		arm_periph_clk: arm-periph-clk {

		arm_periph_clk: clk-m-a9-periphs {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <600000000>;

			compatible = "fixed-factor-clock";



			clocks = <&clk_m_a9>;

			clock-div = <2>;

			clock-mult = <1>;

		};



		/*

		 * A9 PLL.

		 */

		clockgen-a9@92b0000 {

			compatible = "st,clkgen-c32";

			reg = <0x92b0000 0xffff>;



			clockgen_a9_pll: clockgen-a9-pll {

				#clock-cells = <1>;

				compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";



				clocks = <&clk_sysin>;



				clock-output-names = "clockgen-a9-pll-odf";

			};

		};



		/*

		 * ARM CPU related clocks.

		 */

		clk_m_a9: clk-m-a9@92b0000 {

			#clock-cells = <0>;

			compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";

			reg = <0x92b0000 0x10000>;



			clocks = <&clockgen_a9_pll 0>,

				 <&clockgen_a9_pll 0>,

				 <&clk_s_c0_flexgen 13>,

				 <&clk_m_a9_ext2f_div2>;

		};



		/*

		 * ARM Peripheral clock for timers

		 */

		clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {

			#clock-cells = <0>;

			compatible = "fixed-factor-clock";



			clocks = <&clk_s_c0_flexgen 13>;



			clock-output-names = "clk-m-a9-ext2f-div2";



			clock-div = <2>;

			clock-mult = <1>;

		};



		/*
@@ -35,5 +89,238 @@ 
			clock-frequency = <200000000>;

			clock-output-names = "clk-s-icn-reg-0";

		};



		clockgen-a@090ff000 {

			compatible = "st,clkgen-c32";

			reg = <0x90ff000 0x1000>;



			clk_s_a0_pll: clk-s-a0-pll {

				#clock-cells = <1>;

				compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";



				clocks = <&clk_sysin>;



				clock-output-names = "clk-s-a0-pll-ofd-0";

			};



			clk_s_a0_flexgen: clk-s-a0-flexgen {

				compatible = "st,flexgen";



				#clock-cells = <1>;



				clocks = <&clk_s_a0_pll 0>,

					 <&clk_sysin>;



				clock-output-names = "clk-ic-lmi0";

			};

		};



		clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {

			#clock-cells = <1>;

			compatible = "st,stih407-quadfs660-C", "st,quadfs";

			reg = <0x9103000 0x1000>;



			clocks = <&clk_sysin>;



			clock-output-names = "clk-s-c0-fs0-ch0",

					     "clk-s-c0-fs0-ch1",

					     "clk-s-c0-fs0-ch2",

					     "clk-s-c0-fs0-ch3";

		};



		clk_s_c0: clockgen-c@09103000 {

			compatible = "st,clkgen-c32";

			reg = <0x9103000 0x1000>;



			clk_s_c0_pll0: clk-s-c0-pll0 {

				#clock-cells = <1>;

				compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";



				clocks = <&clk_sysin>;



				clock-output-names = "clk-s-c0-pll0-odf-0";

			};



			clk_s_c0_pll1: clk-s-c0-pll1 {

				#clock-cells = <1>;

				compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";



				clocks = <&clk_sysin>;



				clock-output-names = "clk-s-c0-pll1-odf-0";

			};



			clk_s_c0_flexgen: clk-s-c0-flexgen {

				#clock-cells = <1>;

				compatible = "st,flexgen";



				clocks = <&clk_s_c0_pll0 0>,

					 <&clk_s_c0_pll1 0>,

					 <&clk_s_c0_quadfs 0>,

					 <&clk_s_c0_quadfs 1>,

					 <&clk_s_c0_quadfs 2>,

					 <&clk_s_c0_quadfs 3>,

					 <&clk_sysin>;



				clock-output-names = "clk-icn-gpu",

						     "clk-fdma",

						     "clk-nand",

						     "clk-hva",

						     "clk-proc-stfe",

						     "clk-proc-tp",

						     "clk-rx-icn-dmu",

						     "clk-rx-icn-hva",

						     "clk-icn-cpu",

						     "clk-tx-icn-dmu",

						     "clk-mmc-0",

						     "clk-mmc-1",

						     "clk-jpegdec",

						     "clk-ext2fa9",

						     "clk-ic-bdisp-0",

						     "clk-ic-bdisp-1",

						     "clk-pp-dmu",

						     "clk-vid-dmu",

						     "clk-dss-lpc",

						     "clk-st231-aud-0",

						     "clk-st231-gp-1",

						     "clk-st231-dmu",

						     "clk-icn-lmi",

						     "clk-tx-icn-disp-1",

						     "clk-icn-sbc",

						     "clk-stfe-frc2",

						     "clk-eth-phy",

						     "clk-eth-ref-phyclk",

						     "clk-flash-promip",

						     "clk-main-disp",

						     "clk-aux-disp",

						     "clk-compo-dvp";

			};

		};



		clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {

			#clock-cells = <1>;

			compatible = "st,stih407-quadfs660-D", "st,quadfs";

			reg = <0x9104000 0x1000>;



			clocks = <&clk_sysin>;



			clock-output-names = "clk-s-d0-fs0-ch0",

					     "clk-s-d0-fs0-ch1",

					     "clk-s-d0-fs0-ch2",

					     "clk-s-d0-fs0-ch3";

		};



		clockgen-d0@09104000 {

			compatible = "st,clkgen-c32";

			reg = <0x9104000 0x1000>;



			clk_s_d0_flexgen: clk-s-d0-flexgen {

				#clock-cells = <1>;

				compatible = "st,flexgen";



				clocks = <&clk_s_d0_quadfs 0>,

					 <&clk_s_d0_quadfs 1>,

					 <&clk_s_d0_quadfs 2>,

					 <&clk_s_d0_quadfs 3>,

					 <&clk_sysin>;



				clock-output-names = "clk-pcm-0",

						     "clk-pcm-1",

						     "clk-pcm-2",

						     "clk-spdiff";

			};

		};



		clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {

			#clock-cells = <1>;

			compatible = "st,stih407-quadfs660-D", "st,quadfs";

			reg = <0x9106000 0x1000>;



			clocks = <&clk_sysin>;



			clock-output-names = "clk-s-d2-fs0-ch0",

					     "clk-s-d2-fs0-ch1",

					     "clk-s-d2-fs0-ch2",

					     "clk-s-d2-fs0-ch3";

		};



		clk_tmdsout_hdmi: clk-tmdsout-hdmi {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <0>;

		};



		clockgen-d2@x9106000 {

			compatible = "st,clkgen-c32";

			reg = <0x9106000 0x1000>;



			clk_s_d2_flexgen: clk-s-d2-flexgen {

				#clock-cells = <1>;

				compatible = "st,flexgen";



				clocks = <&clk_s_d2_quadfs 0>,

					 <&clk_s_d2_quadfs 1>,

					 <&clk_s_d2_quadfs 2>,

					 <&clk_s_d2_quadfs 3>,

					 <&clk_sysin>,

					 <&clk_sysin>,

					 <&clk_tmdsout_hdmi>;



				clock-output-names = "clk-pix-main-disp",

						     "clk-pix-pip",

						     "clk-pix-gdp1",

						     "clk-pix-gdp2",

						     "clk-pix-gdp3",

						     "clk-pix-gdp4",

						     "clk-pix-aux-disp",

						     "clk-denc",

						     "clk-pix-hddac",

						     "clk-hddac",

						     "clk-sddac",

						     "clk-pix-dvo",

						     "clk-dvo",

						     "clk-pix-hdmi",

						     "clk-tmds-hdmi",

						     "clk-ref-hdmiphy";

						     };

		};



		clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {

			#clock-cells = <1>;

			compatible = "st,stih407-quadfs660-D", "st,quadfs";

			reg = <0x9107000 0x1000>;



			clocks = <&clk_sysin>;



			clock-output-names = "clk-s-d3-fs0-ch0",

					     "clk-s-d3-fs0-ch1",

					     "clk-s-d3-fs0-ch2",

					     "clk-s-d3-fs0-ch3";

		};



		clockgen-d3@9107000 {

			compatible = "st,clkgen-c32";

			reg = <0x9107000 0x1000>;



			clk_s_d3_flexgen: clk-s-d3-flexgen {

				#clock-cells = <1>;

				compatible = "st,flexgen";



				clocks = <&clk_s_d3_quadfs 0>,

					 <&clk_s_d3_quadfs 1>,

					 <&clk_s_d3_quadfs 2>,

					 <&clk_s_d3_quadfs 3>,

					 <&clk_sysin>;



				clock-output-names = "clk-stfe-frc1",

						     "clk-tsout-0",

						     "clk-tsout-1",

						     "clk-mchi",

						     "clk-vsens-compo",

						     "clk-frc1-remote",

						     "clk-lpc-0",

						     "clk-lpc-1";

			};

		};

	};

};

arch/arm/boot/dts/stih407.dtsi

+25 −9
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
 */

#include "stih407-clock.dtsi"

#include "stih407-pinctrl.dtsi"

#include <dt-bindings/reset-controller/stih407-resets.h>

/ {

	#address-cells = <1>;

	#size-cells = <1>;
@@ -63,6 +64,21 @@ 
		ranges;

		compatible = "simple-bus";



		powerdown: powerdown-controller {

			compatible = "st,stih407-powerdown";

			#reset-cells = <1>;

		};



		softreset: softreset-controller {

			compatible = "st,stih407-softreset";

			#reset-cells = <1>;

		};



		picophyreset: picophyreset-controller {

			compatible = "st,stih407-picophyreset";

			#reset-cells = <1>;

		};



		syscfg_sbc: sbc-syscfg@9620000 {

			compatible = "st,stih407-sbc-syscfg", "syscon";

			reg = <0x9620000 0x1000>;
@@ -104,7 +120,7 @@ 
			interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_serial0>;

			clocks = <&clk_ext2f_a9>;

			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;



			status = "disabled";

		};
@@ -115,7 +131,7 @@ 
			interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_serial1>;

			clocks = <&clk_ext2f_a9>;

			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;



			status = "disabled";

		};
@@ -126,7 +142,7 @@ 
			interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_serial2>;

			clocks = <&clk_ext2f_a9>;

			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;



			status = "disabled";

		};
@@ -158,7 +174,7 @@ 
			compatible = "st,comms-ssc4-i2c";

			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;

			reg = <0x9840000 0x110>;

			clocks = <&clk_ext2f_a9>;

			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			clock-names = "ssc";

			clock-frequency = <400000>;

			pinctrl-names = "default";
@@ -171,7 +187,7 @@ 
			compatible = "st,comms-ssc4-i2c";

			reg = <0x9841000 0x110>;

			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_ext2f_a9>;

			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			clock-names = "ssc";

			clock-frequency = <400000>;

			pinctrl-names = "default";
@@ -184,7 +200,7 @@ 
			compatible = "st,comms-ssc4-i2c";

			reg = <0x9842000 0x110>;

			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_ext2f_a9>;

			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			clock-names = "ssc";

			clock-frequency = <400000>;

			pinctrl-names = "default";
@@ -197,7 +213,7 @@ 
			compatible = "st,comms-ssc4-i2c";

			reg = <0x9843000 0x110>;

			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_ext2f_a9>;

			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			clock-names = "ssc";

			clock-frequency = <400000>;

			pinctrl-names = "default";
@@ -210,7 +226,7 @@ 
			compatible = "st,comms-ssc4-i2c";

			reg = <0x9844000 0x110>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_ext2f_a9>;

			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			clock-names = "ssc";

			clock-frequency = <400000>;

			pinctrl-names = "default";
@@ -223,7 +239,7 @@ 
			compatible = "st,comms-ssc4-i2c";

			reg = <0x9845000 0x110>;

			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_ext2f_a9>;

			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			clock-names = "ssc";

			clock-frequency = <400000>;

			pinctrl-names = "default";

arch/arm/boot/dts/stih415-pinctrl.dtsi

+191 −170

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/boot/dts/stih415.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -218,5 +218,17 @@ 
			resets	= <&powerdown STIH415_KEYSCAN_POWERDOWN>,

				  <&softreset STIH415_KEYSCAN_SOFTRESET>;

		};



		mmc0: sdhci@fe81e000 {

			compatible      = "st,sdhci";

			status          = "disabled";

			reg             = <0xfe81e000 0x1000>;

			interrupts      = <GIC_SPI 145 IRQ_TYPE_NONE>;

			interrupt-names = "mmcirq";

			pinctrl-names   = "default";

			pinctrl-0       = <&pinctrl_mmc0>;

			clock-names     = "mmc";

			clocks          = <&clk_s_a1_ls 1>;

		};

	};

};

arch/arm/boot/dts/stih416-b2020.dts

+22 −0
Original line number Diff line number Diff line
@@ -12,4 +12,26 @@ 
/ {

	model = "STiH416 B2020";

	compatible = "st,stih416-b2020", "st,stih416";



	soc {

		mmc1: sdhci@fe81f000 {

			status       = "okay";

			bus-width    = <8>;

			non-removable;

		};



		miphy365x_phy: miphy365x@fe382000 {

			phy_port0: port@fe382000 {

				st,sata-gen = <3>;

			};



			phy_port1: port@fe38a000 {

				st,pcie-tx-pol-inv;

			};

		};



		sata0: sata@fe380000{

			status = "okay";

		};

	};

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE