Unverified Commit 16c8ff57 authored by Jagan Teki's avatar Jagan Teki Committed by Maxime Ripard
Browse files

arm64: dts: allwinner: a64: Add MIPI DSI pipeline 



Add MIPI DSI pipeline for Allwinner A64.

- dsi node, with A64 compatible since it doesn't support
  DSI_SCLK gating unlike A33
- dphy node, with A64 compatible with A33 fallback since
  DPHY on A64 and A33 is similar
- finally, attach the dsi_in to tcon0 for complete MIPI DSI

Signed-off-by: default avatarJagan Teki <jagan@amarulasolutions.com>
Tested-by: default avatarMerlijn Wajer <merlijn@wizzup.org>
Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
parent 59f5e9b9

arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi

+37 −0
Original line number Diff line number Diff line
@@ -367,6 +367,12 @@ 
					#address-cells = <1>;

					#size-cells = <0>;

					reg = <1>;



					tcon0_out_dsi: endpoint@1 {

						reg = <1>;

						remote-endpoint = <&dsi_in_tcon0>;

						allwinner,tcon-channel = <1>;

					};

				};

			};

		};
@@ -1017,6 +1023,37 @@ 
			status = "disabled";

		};



		dsi: dsi@1ca0000 {

			compatible = "allwinner,sun50i-a64-mipi-dsi";

			reg = <0x01ca0000 0x1000>;

			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_MIPI_DSI>;

			resets = <&ccu RST_BUS_MIPI_DSI>;

			phys = <&dphy>;

			phy-names = "dphy";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;



			port {

				dsi_in_tcon0: endpoint {

					remote-endpoint = <&tcon0_out_dsi>;

				};

			};

		};



		dphy: d-phy@1ca1000 {

			compatible = "allwinner,sun50i-a64-mipi-dphy",

				     "allwinner,sun6i-a31-mipi-dphy";

			reg = <0x01ca1000 0x1000>;

			clocks = <&ccu CLK_BUS_MIPI_DSI>,

				 <&ccu CLK_DSI_DPHY>;

			clock-names = "bus", "mod";

			resets = <&ccu RST_BUS_MIPI_DSI>;

			status = "disabled";

			#phy-cells = <0>;

		};



		hdmi: hdmi@1ee0000 {

			compatible = "allwinner,sun50i-a64-dw-hdmi",

				     "allwinner,sun8i-a83t-dw-hdmi";

CRA Git | Maintained and supported by SUSTech CRA and CCSE