cxl: Fix NULL dereference in cxl_context_init() on PowerVM guests (16479337) · Commits · 戴 / test

Commit ("cxl: Workaround PE=0 hardware limitation in Mellanox CX4") added a "min_pe" field to struct cxl_service_layer_ops, to allow us to work around a Mellanox CX-4 hardware limitation. When allocating the PE number in cxl_context_init(), we read from ctx->afu->adapter->native->sl_ops->min_pe to get the minimum PE number. Unsurprisingly, in a PowerVM guest ctx->afu->adapter->native is NULL, and guests don't have a cxl_service_layer_ops struct anywhere. Move min_pe from struct cxl_service_layer_ops to struct cxl so it's accessible in both native and PowerVM environments. For the Mellanox CX-4, set the min_pe value in set_sl_ops(). Fixes: ("cxl: Workaround PE=0 hardware limitation in Mellanox CX4") Reported-by:

Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by:

Andrew Donnellan <andrew.donnellan@au1.ibm.com> Acked-by:

Ian Munsie <imunsie@au1.ibm.com> Reviewed-by:

Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by:

Michael Ellerman <mpe@ellerman.id.au>

drivers/misc/cxl/context.c

+1 −2

Original line number	Diff line number	Diff line
		@@ -90,8 +90,7 @@ int cxl_context_init(struct cxl_context ctx, struct cxl_afu afu, bool master,
		*/
		mutex_lock(&afu->contexts_lock);
		idr_preload(GFP_KERNEL);
		i = idr_alloc(&ctx->afu->contexts_idr, ctx,
		ctx->afu->adapter->native->sl_ops->min_pe,
		i = idr_alloc(&ctx->afu->contexts_idr, ctx, ctx->afu->adapter->min_pe,
		ctx->afu->num_procs, GFP_NOWAIT);
		idr_preload_end();
		mutex_unlock(&afu->contexts_lock);

drivers/misc/cxl/cxl.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -561,7 +561,6 @@ struct cxl_service_layer_ops {
		u64 (timebase_read)(struct cxl adapter);
		int capi_mode;
		bool needs_reset_before_disable;
		int min_pe;
		};

		struct cxl_native {
		@@ -603,6 +602,7 @@ struct cxl {
		struct bin_attribute cxl_attr;
		int adapter_num;
		int user_irqs;
		int min_pe;
		u64 ps_size;
		u16 psl_rev;
		u16 base_image;

drivers/misc/cxl/pci.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -1521,14 +1521,15 @@ static const struct cxl_service_layer_ops xsl_ops = {
		.write_timebase_ctrl = write_timebase_ctrl_xsl,
		.timebase_read = timebase_read_xsl,
		.capi_mode = OPAL_PHB_CAPI_MODE_DMA,
		.min_pe = 1, /* Workaround for Mellanox CX4 HW bug */
		};

		static void set_sl_ops(struct cxl adapter, struct pci_dev dev)
		{
		if (dev->vendor == PCI_VENDOR_ID_MELLANOX && dev->device == 0x1013) {
		/* Mellanox CX-4 */
		dev_info(&adapter->dev, "Device uses an XSL\n");
		adapter->native->sl_ops = &xsl_ops;
		adapter->min_pe = 1; /* Workaround for CX-4 hardware bug */
		} else {
		dev_info(&adapter->dev, "Device uses a PSL\n");
		adapter->native->sl_ops = &psl_ops;

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