Commit f67a6722 authored by Ian Munsie's avatar Ian Munsie Committed by Michael Ellerman
Browse files

cxl: Workaround PE=0 hardware limitation in Mellanox CX4 



The CX4 card cannot cope with a context with PE=0 due to a hardware
limitation, resulting in:

[   34.166577] command failed, status limits exceeded(0x8), syndrome 0x5a7939
[   34.166580] mlx5_core 0000:01:00.1: Failed allocating uar, aborting

Since the kernel API allocates a default context very early during
device init that will almost certainly get Process Element ID 0 there is
no easy way for us to extend the API to allow the Mellanox to inform us
of this limitation ahead of time.

Instead, work around the issue by extending the XSL structure to include
a minimum PE to allocate. Although the bug is not in the XSL, it is the
easiest place to work around this limitation given that the CX4 is
currently the only card that uses an XSL.

Signed-off-by: default avatarIan Munsie <imunsie@au1.ibm.com>
Reviewed-by: default avatarAndrew Donnellan <andrew.donnellan@au1.ibm.com>
Reviewed-by: default avatarFrederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent a2f67d5e

drivers/misc/cxl/context.c

+2 −1
Original line number Original line Diff line number Diff line
@@ -90,7 +90,8 @@ int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master, 
	 */

	 */

	mutex_lock(&afu->contexts_lock);

	mutex_lock(&afu->contexts_lock);

	idr_preload(GFP_KERNEL);

	idr_preload(GFP_KERNEL);

	i = idr_alloc(&ctx->afu->contexts_idr, ctx, 0,

	i = idr_alloc(&ctx->afu->contexts_idr, ctx,

		      ctx->afu->adapter->native->sl_ops->min_pe,

		      ctx->afu->num_procs, GFP_NOWAIT);

		      ctx->afu->num_procs, GFP_NOWAIT);

	idr_preload_end();

	idr_preload_end();

	mutex_unlock(&afu->contexts_lock);

	mutex_unlock(&afu->contexts_lock);

drivers/misc/cxl/cxl.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -561,6 +561,7 @@ struct cxl_service_layer_ops { 
	u64 (*timebase_read)(struct cxl *adapter);

	u64 (*timebase_read)(struct cxl *adapter);

	int capi_mode;

	int capi_mode;

	bool needs_reset_before_disable;

	bool needs_reset_before_disable;

	int min_pe;

};

};





struct cxl_native {

struct cxl_native {

drivers/misc/cxl/pci.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -1321,6 +1321,7 @@ static const struct cxl_service_layer_ops xsl_ops = { 
	.write_timebase_ctrl = write_timebase_ctrl_xsl,

	.write_timebase_ctrl = write_timebase_ctrl_xsl,

	.timebase_read = timebase_read_xsl,

	.timebase_read = timebase_read_xsl,

	.capi_mode = OPAL_PHB_CAPI_MODE_DMA,

	.capi_mode = OPAL_PHB_CAPI_MODE_DMA,

	.min_pe = 1, /* Workaround for Mellanox CX4 HW bug */

};

};





static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev)

static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev)

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