Commit 1371a80c authored Jul 20, 2020 by David Clear Committed by Tudor Ambarus Jul 27, 2020

mtd: spi-nor: micron: Add SPI_NOR_DUAL_READ flag on mt25qu02g



The Micron mt25qu02g supports both x2 and x4 transactions. Add the
SPI_NOR_DUAL_READ flag to its spi_nor_ids[] table entry.

Tested on Pensando SoC hardware with a cadence quadspi controller
via drivers/spi/spi-cadence-quadspi.c, in x2 mode at 50MHz.
  - random data write, erase, read   - verified erase operations
  - random data write, read/compare  - verified write/read operations

Signed-off-by: David Clear <dac2@pensando.io>
Acked-by: Shannon Nelson <snelson@pensando.io>
Link: https://lore.kernel.org/r/20200720163656.38006-3-dac2@pensando.io


Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>

parent 48029e62

drivers/mtd/spi-nor/micron-st.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -71,8 +71,8 @@ static const struct flash_info st_parts[] = {
		SECT_4K \| USE_FSR \| SPI_NOR_QUAD_READ \|
		NO_CHIP_ERASE) },
		{ "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096,
		SECT_4K \| USE_FSR \| SPI_NOR_QUAD_READ \|
		NO_CHIP_ERASE) },
		SECT_4K \| USE_FSR \| SPI_NOR_DUAL_READ \|
		SPI_NOR_QUAD_READ \| NO_CHIP_ERASE) },

		{ "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
		{ "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },

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