Commit 48029e62 authored Jul 20, 2020 by David Clear Committed by Tudor Ambarus Jul 27, 2020

mtd: spi-nor: macronix: Add support for mx66u2g45g



The Macronix mx66u2g45g is a 1.8V, 2Gbit (256MB) device that
supports x1, x2, or x4 operation.

Tested on Pensando SoC hardware with a cadence quadspi controller
via drivers/spi/spi-cadence-quadspi.c, in x2 mode at 50MHz.
  - random data write, erase, read   - verified erase operations
  - random data write, read/compare  - verified write/read operations

Signed-off-by: David Clear <dac2@pensando.io>
Acked-by: Shannon Nelson <snelson@pensando.io>
Link: https://lore.kernel.org/r/20200720163656.38006-2-dac2@pensando.io


Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>

parent 44a80df4

drivers/mtd/spi-nor/macronix.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -87,6 +87,9 @@ static const struct flash_info macronix_parts[] = {
		SPI_NOR_QUAD_READ) },
		{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048,
		SPI_NOR_QUAD_READ) },
		{ "mx66u2g45g", INFO(0xc2253c, 0, 64 * 1024, 4096,
		SECT_4K \| SPI_NOR_DUAL_READ \|
		SPI_NOR_QUAD_READ \| SPI_NOR_4B_OPCODES) },
		};

		static void macronix_default_init(struct spi_nor *nor)

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