drm/i915: DSPFW and BLC regs are in the display offset range

#define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)

/* Backlight control */

#define BLC_PWM_CTL2		0x61250 /* 965+ only */

#define BLC_PWM_CTL2	(dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */

#define   BLM_PWM_ENABLE		(1 << 31)

#define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */

#define   BLM_PIPE_SELECT		(1 << 29)

#define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)

#define   BLM_PHASE_IN_INCR_SHIFT	(0)

#define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)

#define BLC_PWM_CTL		0x61254

#define BLC_PWM_CTL	(dev_priv->info->display_mmio_offset + 0x61254)

/*

 * This is the most significant 15 bits of the number of backlight cycles in a

 * complete cycle of the modulated backlight control.

#define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)

#define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */

#define BLC_HIST_CTL		0x61260

#define BLC_HIST_CTL	(dev_priv->info->display_mmio_offset + 0x61260)

/* New registers for PCH-split platforms. Safe where new bits show up, the

 * register layout machtes with gen4 BLC_PWM_CTL[12]. */

#define   DSPFW_HPLL_CURSOR_SHIFT	16

#define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)

#define   DSPFW_HPLL_SR_MASK		(0x1ff)

#define DSPFW4			(dev_priv->info->display_mmio_offset + 0x70070)

#define DSPFW7			(dev_priv->info->display_mmio_offset + 0x7007c)

/* drain latency register values*/

#define DRAIN_LATENCY_PRECISION_32	32