drm/i915: set conservative clock gating values on VLV v2 (4e8c84a5) · Commits · 戴 / test

We'll re-enable select bits as needed after testing and power measurement. v2: split out wake handling bits (Jani) Signed-off-by:

drivers/gpu/drm/i915/intel_pm.c

+10 −1

Original line number	Diff line number	Diff line
		@@ -3987,7 +3987,16 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
		* Disable clock gating on th GCFG unit to prevent a delay
		* in the reporting of vblank events.
		*/
		I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
		I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);

		/* Conservative clock gating settings for now */
		I915_WRITE(0x9400, 0xffffffff);
		I915_WRITE(0x9404, 0xffffffff);
		I915_WRITE(0x9408, 0xffffffff);
		I915_WRITE(0x940c, 0xffffffff);
		I915_WRITE(0x9410, 0xffffffff);
		I915_WRITE(0x9414, 0xffffffff);
		I915_WRITE(0x9418, 0xffffffff);
		}

		static void g4x_init_clock_gating(struct drm_device *dev)