Commit 123e8b4f authored by Matthias Brugger's avatar Matthias Brugger Committed by Matthias Brugger
Browse files

soc: mediatek: pm-domains: Add subsystem clocks 



For the bus protection operations, some subsystem clocks need to be enabled
before releasing the protection. This patch identifies the subsystem clocks
by it's name.

Suggested-by: default avatarWeiyi Lu <weiyi.lu@mediatek.com>
[Adapted the patch to the mtk-pm-domains driver]
Signed-off-by: default avatarMatthias Brugger <mbrugger@suse.com>
Signed-off-by: default avatarEnric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201030113622.201188-9-enric.balletbo@collabora.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 58a17e31

drivers/soc/mediatek/mtk-pm-domains.c

+70 −11
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 * Copyright (c) 2020 Collabora Ltd.

 */

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/init.h>

#include <linux/io.h>

#include <linux/iopoll.h>
@@ -33,6 +34,8 @@ struct scpsys_domain { 
	struct scpsys *scpsys;

	int num_clks;

	struct clk_bulk_data *clks;

	int num_subsys_clks;

	struct clk_bulk_data *subsys_clks;

	struct regmap *infracfg;

	struct regmap *smi;

};
@@ -204,9 +207,13 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) 
	regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);

	regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);



	ret = clk_bulk_enable(pd->num_subsys_clks, pd->subsys_clks);

	if (ret)

		goto err_pwr_ack;



	ret = scpsys_sram_enable(pd);

	if (ret < 0)

		goto err_pwr_ack;

		goto err_disable_subsys_clks;



	ret = scpsys_bus_protect_disable(pd);

	if (ret < 0)
@@ -216,6 +223,8 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) 


err_disable_sram:

	scpsys_sram_disable(pd);

err_disable_subsys_clks:

	clk_bulk_disable(pd->num_subsys_clks, pd->subsys_clks);

err_pwr_ack:

	clk_bulk_disable(pd->num_clks, pd->clks);

	return ret;
@@ -236,6 +245,8 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) 
	if (ret < 0)

		return ret;



	clk_bulk_disable(pd->num_subsys_clks, pd->subsys_clks);



	/* subsys power off */

	regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);

	regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);
@@ -259,7 +270,11 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no 
{

	const struct scpsys_domain_data *domain_data;

	struct scpsys_domain *pd;

	int i, ret;

	struct property *prop;

	const char *clk_name;

	int i, ret, num_clks;

	struct clk *clk;

	int clk_ind = 0;

	u32 id;



	ret = of_property_read_u32(node, "reg", &id);
@@ -295,25 +310,62 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no 
	if (IS_ERR(pd->smi))

		return ERR_CAST(pd->smi);



	pd->num_clks = of_clk_get_parent_count(node);

	if (pd->num_clks > 0) {

	num_clks = of_clk_get_parent_count(node);

	if (num_clks > 0) {

		/* Calculate number of subsys_clks */

		of_property_for_each_string(node, "clock-names", prop, clk_name) {

			char *subsys;



			subsys = strchr(clk_name, '-');

			if (subsys)

				pd->num_subsys_clks++;

			else

				pd->num_clks++;

		}



		pd->clks = devm_kcalloc(scpsys->dev, pd->num_clks, sizeof(*pd->clks), GFP_KERNEL);

		if (!pd->clks)

			return ERR_PTR(-ENOMEM);



		pd->subsys_clks = devm_kcalloc(scpsys->dev, pd->num_subsys_clks,

					       sizeof(*pd->subsys_clks), GFP_KERNEL);

		if (!pd->subsys_clks)

			return ERR_PTR(-ENOMEM);



	}



	for (i = 0; i < pd->num_clks; i++) {

		pd->clks[i].clk = of_clk_get(node, i);

		if (IS_ERR(pd->clks[i].clk)) {

			dev_err(scpsys->dev, "%pOF: failed to get clk at index %d\n",

				node, i);

			return ERR_PTR(-EINVAL);

		clk = of_clk_get(node, i);

		if (IS_ERR(clk)) {

			ret = PTR_ERR(clk);

			dev_err_probe(scpsys->dev, ret,

				      "%pOF: failed to get clk at index %d: %d\n", node, i, ret);

			goto err_put_clocks;

		}



		pd->clks[clk_ind++].clk = clk;

	}



	for (i = 0; i < pd->num_subsys_clks; i++) {

		clk = of_clk_get(node, i + clk_ind);

		if (IS_ERR(clk)) {

			ret = PTR_ERR(clk);

			dev_err_probe(scpsys->dev, ret,

				      "%pOF: failed to get clk at index %d: %d\n", node,

				      i + clk_ind, ret);

			goto err_put_subsys_clocks;

		}



		pd->subsys_clks[i].clk = clk;

	}



	ret = clk_bulk_prepare(pd->num_clks, pd->clks);

	if (ret)

		goto err_put_clocks;

		goto err_put_subsys_clocks;



	ret = clk_bulk_prepare(pd->num_subsys_clks, pd->subsys_clks);

	if (ret)

		goto err_unprepare_clocks;



	/*

	 * Initially turn on all domains to make the domains usable
@@ -331,7 +383,7 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no 
		ret = -EINVAL;

		dev_err(scpsys->dev,

			"power domain with id %d already exists, check your device-tree\n", id);

		goto err_unprepare_clocks;

		goto err_unprepare_subsys_clocks;

	}



	pd->genpd.name = node->name;
@@ -343,8 +395,12 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no 


	return scpsys->pd_data.domains[id];



err_unprepare_subsys_clocks:

	clk_bulk_unprepare(pd->num_subsys_clks, pd->subsys_clks);

err_unprepare_clocks:

	clk_bulk_unprepare(pd->num_clks, pd->clks);

err_put_subsys_clocks:

	clk_bulk_put(pd->num_subsys_clks, pd->subsys_clks);

err_put_clocks:

	clk_bulk_put(pd->num_clks, pd->clks);

	return ERR_PTR(ret);
@@ -421,6 +477,9 @@ static void scpsys_remove_one_domain(struct scpsys_domain *pd) 


	clk_bulk_unprepare(pd->num_clks, pd->clks);

	clk_bulk_put(pd->num_clks, pd->clks);



	clk_bulk_unprepare(pd->num_subsys_clks, pd->subsys_clks);

	clk_bulk_put(pd->num_subsys_clks, pd->subsys_clks);

}



static void scpsys_domain_cleanup(struct scpsys *scpsys)

drivers/soc/mediatek/mtk-pm-domains.h

+2 −0
Original line number Diff line number Diff line
@@ -63,6 +63,8 @@ struct scpsys_bus_prot_data { 
	bool bus_prot_reg_update;

};



#define MAX_SUBSYS_CLKS 10



/**

 * struct scpsys_domain_data - scp domain data for power on/off flow

 * @sta_mask: The mask for power on/off status bit.

CRA Git | Maintained and supported by SUSTech CRA and CCSE