soc: mediatek: pm-domains: Add extra sram control

#define PWR_ON_BIT			BIT(2)

#define PWR_ON_2ND_BIT			BIT(3)

#define PWR_CLK_DIS_BIT			BIT(4)

#define PWR_SRAM_CLKISO_BIT		BIT(5)

#define PWR_SRAM_ISOINT_B_BIT		BIT(6)

struct scpsys_domain {

	struct generic_pm_domain genpd;

	u32 pdn_ack = pd->data->sram_pdn_ack_bits;

	struct scpsys *scpsys = pd->scpsys;

	unsigned int tmp;

	int ret;

	regmap_clear_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_bits);

	/* Either wait until SRAM_PDN_ACK all 1 or 0 */

	return regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp,

	ret = regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp,

				       (tmp & pdn_ack) == 0, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);

	if (ret < 0)

		return ret;

	if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_ISO)) {

		regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_SRAM_ISOINT_B_BIT);

		udelay(1);

		regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_SRAM_CLKISO_BIT);

	}

	return 0;

}

static int scpsys_sram_disable(struct scpsys_domain *pd)

	struct scpsys *scpsys = pd->scpsys;

	unsigned int tmp;

	if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_ISO)) {

		regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_SRAM_CLKISO_BIT);

		udelay(1);

		regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_SRAM_ISOINT_B_BIT);

	}

	regmap_set_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_bits);

	/* Either wait until SRAM_PDN_ACK all 1 or 0 */

#define MTK_SCPD_ACTIVE_WAKEUP		BIT(0)

#define MTK_SCPD_FWAIT_SRAM		BIT(1)

#define MTK_SCPD_SRAM_ISO		BIT(2)

#define MTK_SCPD_CAPS(_scpd, _x)	((_scpd)->data->caps & (_x))

#define SPM_VDE_PWR_CON			0x0210