Commit 10f33d39 authored by Hui Tang's avatar Hui Tang Committed by Herbert Xu
Browse files

crypto: hisilicon/hpre - disable FLR triggered by hardware 



for Hi1620 hardware, we should disable these hardware flr:
1. BME_FLR - bit 7,
2. PM_FLR - bit 11,
3. SRIOV_FLR - bit 12,
Or HPRE may goto D3 state, when we bind and unbind HPRE quickly,
as it does FLR triggered by BME/PM/SRIOV.

Fixes: c8b4b477("crypto: hisilicon - add HiSilicon HPRE accelerator")
Signed-off-by: default avatarHui Tang <tanghui20@huawei.com>
Signed-off-by: default avatarMeng Yu <yumeng18@huawei.com>
Reviewed-by: default avatarZaibo Xu <xuzaibo@huawei.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent dadbe4c1

drivers/crypto/hisilicon/hpre/hpre_main.c

+22 −4
Original line number Diff line number Diff line
@@ -82,6 +82,10 @@ 
#define HPRE_CORE_ECC_2BIT_ERR		BIT(1)

#define HPRE_OOO_ECC_2BIT_ERR		BIT(5)



#define HPRE_QM_BME_FLR			BIT(7)

#define HPRE_QM_PM_FLR			BIT(11)

#define HPRE_QM_SRIOV_FLR		BIT(12)



#define HPRE_VIA_MSI_DSM		1

#define HPRE_SQE_MASK_OFFSET		8

#define HPRE_SQE_MASK_LEN		24
@@ -230,6 +234,22 @@ static int hpre_cfg_by_dsm(struct hisi_qm *qm) 
	return 0;

}



/*

 * For Hi1620, we shoul disable FLR triggered by hardware (BME/PM/SRIOV).

 * Or it may stay in D3 state when we bind and unbind hpre quickly,

 * as it does FLR triggered by hardware.

 */

static void disable_flr_of_bme(struct hisi_qm *qm)

{

	u32 val;



	val = readl(HPRE_ADDR(qm, QM_PEH_AXUSER_CFG));

	val &= ~(HPRE_QM_BME_FLR | HPRE_QM_SRIOV_FLR);

	val |= HPRE_QM_PM_FLR;

	writel(val, HPRE_ADDR(qm, QM_PEH_AXUSER_CFG));

	writel(PEH_AXUSER_CFG_ENABLE, HPRE_ADDR(qm, QM_PEH_AXUSER_CFG_ENABLE));

}



static int hpre_set_user_domain_and_cache(struct hisi_qm *qm)

{

	struct device *dev = &qm->pdev->dev;
@@ -241,10 +261,6 @@ static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) 
	writel(HPRE_QM_USR_CFG_MASK, HPRE_ADDR(qm, QM_AWUSER_M_CFG_ENABLE));

	writel_relaxed(HPRE_QM_AXI_CFG_MASK, HPRE_ADDR(qm, QM_AXI_M_CFG));



	/* disable FLR triggered by BME(bus master enable) */

	writel(PEH_AXUSER_CFG, HPRE_ADDR(qm, QM_PEH_AXUSER_CFG));

	writel(PEH_AXUSER_CFG_ENABLE, HPRE_ADDR(qm, QM_PEH_AXUSER_CFG_ENABLE));



	/* HPRE need more time, we close this interrupt */

	val = readl_relaxed(HPRE_ADDR(qm, HPRE_QM_ABNML_INT_MASK));

	val |= BIT(HPRE_TIMEOUT_ABNML_BIT);
@@ -295,6 +311,8 @@ static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) 
	if (ret)

		dev_err(dev, "acpi_evaluate_dsm err.\n");



	disable_flr_of_bme(qm);



	return ret;

}

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