crypto: hisilicon - add HiSilicon HPRE accelerator

	select SG_SPLIT

	help

	  Support for HiSilicon ZIP Driver

config CRYPTO_DEV_HISI_HPRE

	tristate "Support for HISI HPRE accelerator"

	depends on PCI && PCI_MSI

	depends on ARM64 || (COMPILE_TEST && 64BIT)

	select CRYPTO_DEV_HISI_QM

	select CRYPTO_DH

	select CRYPTO_RSA

	help

	  Support for HiSilicon HPRE(High Performance RSA Engine)

	  accelerator, which can accelerate RSA and DH algorithms.

# SPDX-License-Identifier: GPL-2.0

obj-$(CONFIG_CRYPTO_DEV_HISI_HPRE) += hpre/

obj-$(CONFIG_CRYPTO_DEV_HISI_SEC) += sec/

obj-$(CONFIG_CRYPTO_DEV_HISI_QM) += hisi_qm.o

hisi_qm-objs = qm.o sgl.o

obj-$(CONFIG_CRYPTO_DEV_HISI_HPRE) += hisi_hpre.o

hisi_hpre-objs = hpre_main.o hpre_crypto.o

/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright (c) 2019 HiSilicon Limited. */

#ifndef __HISI_HPRE_H

#define __HISI_HPRE_H

#include <linux/list.h>

#include "../qm.h"

#define HPRE_SQE_SIZE			sizeof(struct hpre_sqe)

#define HPRE_PF_DEF_Q_NUM		64

#define HPRE_PF_DEF_Q_BASE		0

#define HPRE_CLUSTERS_NUM		4

struct hpre {

	struct hisi_qm qm;

	struct list_head list;

	unsigned long status;

};

enum hpre_alg_type {

	HPRE_ALG_NC_NCRT = 0x0,

	HPRE_ALG_NC_CRT = 0x1,

	HPRE_ALG_KG_STD = 0x2,

	HPRE_ALG_KG_CRT = 0x3,

	HPRE_ALG_DH_G2 = 0x4,

	HPRE_ALG_DH = 0x5,

};

struct hpre_sqe {

	__le32 dw0;

	__u8 task_len1;

	__u8 task_len2;

	__u8 mrttest_num;

	__u8 resv1;

	__le64 key;

	__le64 in;

	__le64 out;

	__le16 tag;

	__le16 resv2;

#define _HPRE_SQE_ALIGN_EXT	7

	__le32 rsvd1[_HPRE_SQE_ALIGN_EXT];

};

struct hpre *hpre_find_device(int node);

int hpre_algs_register(void);

void hpre_algs_unregister(void);

#endif