Commit 1004165f authored by Ganesan Ramalingam's avatar Ganesan Ramalingam Committed by Ralf Baechle
Browse files

MIPS: Netlogic: USB support for XLP 



The XLP USB controller appears as a device on the internal SoC PCIe
bus, the block has 2 EHCI blocks and 4 OHCI blocks. Change are to:

* Add files netlogic/xlp/usb-init.c and asm/netlogic/xlp-hal/usb.h
  to initialize the USB controller and define PCI fixups. The PCI
  fixups are to setup interrupts and DMA mask.
* Update include/asm/xlp-hal/{iomap.h,pic.h,xlp.h} to add interrupt
  mapping for EHCI/OHCI interrupts.

Signed-off-by: default avatarGanesan Ramalingam <ganesanr@netlogicmicro.com>
Signed-off-by: default avatarJayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3756/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 9bac624b

arch/mips/include/asm/netlogic/xlp-hal/iomap.h

+1 −1
Original line number Diff line number Diff line
@@ -132,7 +132,7 @@ 
#define	PCI_DEVICE_ID_NLM_PIC		0x1003

#define	PCI_DEVICE_ID_NLM_PCIE		0x1004

#define	PCI_DEVICE_ID_NLM_EHCI		0x1007

#define	PCI_DEVICE_ID_NLM_ILK		0x1008

#define	PCI_DEVICE_ID_NLM_OHCI		0x1008

#define	PCI_DEVICE_ID_NLM_NAE		0x1009

#define	PCI_DEVICE_ID_NLM_POE		0x100A

#define	PCI_DEVICE_ID_NLM_FMN		0x100B

arch/mips/include/asm/netlogic/xlp-hal/pic.h

+4 −0
Original line number Diff line number Diff line
@@ -201,7 +201,11 @@ 
#define PIC_NUM_USB_IRTS		6

#define PIC_IRT_USB_0_INDEX		115

#define PIC_IRT_EHCI_0_INDEX		115

#define PIC_IRT_OHCI_0_INDEX		116

#define PIC_IRT_OHCI_1_INDEX		117

#define PIC_IRT_EHCI_1_INDEX		118

#define PIC_IRT_OHCI_2_INDEX		119

#define PIC_IRT_OHCI_3_INDEX		120

#define PIC_IRT_USB_INDEX(num)		((num) + PIC_IRT_USB_0_INDEX)

/* 115 to 120 */

#define PIC_IRT_GDX_INDEX		121

arch/mips/include/asm/netlogic/xlp-hal/usb.h

0 → 100644
+64 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2003-2012 Broadcom Corporation

 * All Rights Reserved

 *

 * This software is available to you under a choice of one of two

 * licenses.  You may choose to be licensed under the terms of the GNU

 * General Public License (GPL) Version 2, available from the file

 * COPYING in the main directory of this source tree, or the Broadcom

 * license below:

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 *

 * 1. Redistributions of source code must retain the above copyright

 *    notice, this list of conditions and the following disclaimer.

 * 2. Redistributions in binary form must reproduce the above copyright

 *    notice, this list of conditions and the following disclaimer in

 *    the documentation and/or other materials provided with the

 *    distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR

 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE

 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR

 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,

 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE

 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN

 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#ifndef __NLM_HAL_USB_H__

#define __NLM_HAL_USB_H__



#define USB_CTL_0			0x01

#define USB_PHY_0			0x0A

#define USB_PHY_RESET			0x01

#define USB_PHY_PORT_RESET_0		0x10

#define USB_PHY_PORT_RESET_1		0x20

#define USB_CONTROLLER_RESET		0x01

#define USB_INT_STATUS			0x0E

#define USB_INT_EN			0x0F

#define USB_PHY_INTERRUPT_EN		0x01

#define USB_OHCI_INTERRUPT_EN		0x02

#define USB_OHCI_INTERRUPT1_EN		0x04

#define USB_OHCI_INTERRUPT2_EN		0x08

#define USB_CTRL_INTERRUPT_EN		0x10



#ifndef __ASSEMBLY__



#define nlm_read_usb_reg(b, r)			nlm_read_reg(b, r)

#define nlm_write_usb_reg(b, r, v)		nlm_write_reg(b, r, v)

#define nlm_get_usb_pcibase(node, inst)		\

	nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst))

#define nlm_get_usb_hcd_base(node, inst)	\

	nlm_xkphys_map_pcibar0(nlm_get_usb_pcibase(node, inst))

#define nlm_get_usb_regbase(node, inst)		\

	(nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)



#endif

#endif /* __NLM_HAL_USB_H__ */

arch/mips/include/asm/netlogic/xlp-hal/xlp.h

+6 −0
Original line number Diff line number Diff line
@@ -41,6 +41,12 @@ 
#define PIC_PCIE_LINK_1_IRQ		20

#define PIC_PCIE_LINK_2_IRQ		21

#define PIC_PCIE_LINK_3_IRQ		22

#define PIC_EHCI_0_IRQ			23

#define PIC_EHCI_1_IRQ			24

#define PIC_OHCI_0_IRQ			25

#define PIC_OHCI_1_IRQ			26

#define PIC_OHCI_2_IRQ			27

#define PIC_OHCI_3_IRQ			28



#ifndef __ASSEMBLY__

arch/mips/netlogic/xlp/Makefile

+1 −0
Original line number Diff line number Diff line 
obj-y				+= setup.o platform.o nlm_hal.o

obj-$(CONFIG_SMP)		+= wakeup.o

obj-$(CONFIG_USB)		+= usb-init.o

CRA Git | Maintained and supported by SUSTech CRA and CCSE