Commit 9bac624b authored by Ganesan Ramalingam's avatar Ganesan Ramalingam Committed by Ralf Baechle
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MIPS: Netlogic: XLP PCIe controller support. 



Adds support for the XLP on-chip PCIe controller. On XLP, the
on-chip devices(including the 4 PCIe links) appear in the PCIe
configuration space of the XLP as PCI devices.

The changes are to initialize and register the PCIe controller,
enable hardware byte swap in the PCIe IO and MEM space, and to
enable PCIe interrupts.

Signed-off-by: default avatarGanesan Ramalingam <ganesanr@netlogicmicro.com>
Signed-off-by: default avatarJayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3760/
Patchwork: https://patchwork.linux-mips.org/patch/4104/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 77c8da01

arch/mips/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -801,7 +801,6 @@ config NLM_XLP_BOARD 
	select SYS_HAS_CPU_XLP

	select SYS_SUPPORTS_SMP

	select HW_HAS_PCI

	select SWAP_IO_SPACE

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL

	select 64BIT_PHYS_ADDR

arch/mips/include/asm/netlogic/xlp-hal/iomap.h

+3 −0
Original line number Diff line number Diff line
@@ -36,6 +36,9 @@ 
#define __NLM_HAL_IOMAP_H__



#define XLP_DEFAULT_IO_BASE             0x18000000

#define XLP_DEFAULT_PCI_ECFG_BASE	XLP_DEFAULT_IO_BASE

#define XLP_DEFAULT_PCI_CFG_BASE	0x1c000000



#define NMI_BASE			0xbfc00000

#define	XLP_IO_CLK			133333333

arch/mips/include/asm/netlogic/xlp-hal/pcibus.h

0 → 100644
+76 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2003-2012 Broadcom Corporation

 * All Rights Reserved

 *

 * This software is available to you under a choice of one of two

 * licenses.  You may choose to be licensed under the terms of the GNU

 * General Public License (GPL) Version 2, available from the file

 * COPYING in the main directory of this source tree, or the Broadcom

 * license below:

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 *

 * 1. Redistributions of source code must retain the above copyright

 *    notice, this list of conditions and the following disclaimer.

 * 2. Redistributions in binary form must reproduce the above copyright

 *    notice, this list of conditions and the following disclaimer in

 *    the documentation and/or other materials provided with the

 *    distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR

 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE

 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR

 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,

 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE

 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN

 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#ifndef __NLM_HAL_PCIBUS_H__

#define	__NLM_HAL_PCIBUS_H__



/* PCIE Memory and IO regions */

#define	PCIE_MEM_BASE			0xd0000000ULL

#define	PCIE_MEM_LIMIT			0xdfffffffULL

#define	PCIE_IO_BASE			0x14000000ULL

#define	PCIE_IO_LIMIT			0x15ffffffULL



#define	PCIE_BRIDGE_CMD			0x1

#define	PCIE_BRIDGE_MSI_CAP		0x14

#define	PCIE_BRIDGE_MSI_ADDRL		0x15

#define	PCIE_BRIDGE_MSI_ADDRH		0x16

#define	PCIE_BRIDGE_MSI_DATA		0x17



/* XLP Global PCIE configuration space registers */

#define	PCIE_BYTE_SWAP_MEM_BASE		0x247

#define	PCIE_BYTE_SWAP_MEM_LIM		0x248

#define	PCIE_BYTE_SWAP_IO_BASE		0x249

#define	PCIE_BYTE_SWAP_IO_LIM		0x24A

#define	PCIE_MSI_STATUS			0x25A

#define	PCIE_MSI_EN			0x25B

#define	PCIE_INT_EN0			0x261



/* PCIE_MSI_EN */

#define	PCIE_MSI_VECTOR_INT_EN		0xFFFFFFFF



/* PCIE_INT_EN0 */

#define	PCIE_MSI_INT_EN			(1 << 9)



#ifndef __ASSEMBLY__



#define	nlm_read_pcie_reg(b, r)		nlm_read_reg(b, r)

#define	nlm_write_pcie_reg(b, r, v)	nlm_write_reg(b, r, v)

#define	nlm_get_pcie_base(node, inst)	\

			nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst))

#define	nlm_get_pcie_regbase(node, inst)	\

			(nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ)



int xlp_pcie_link_irt(int link);

#endif

#endif /* __NLM_HAL_PCIBUS_H__ */

arch/mips/include/asm/netlogic/xlp-hal/xlp.h

+6 −2
Original line number Diff line number Diff line
@@ -37,6 +37,10 @@ 


#define PIC_UART_0_IRQ			17

#define PIC_UART_1_IRQ			18

#define PIC_PCIE_LINK_0_IRQ		19

#define PIC_PCIE_LINK_1_IRQ		20

#define PIC_PCIE_LINK_2_IRQ		21

#define PIC_PCIE_LINK_3_IRQ		22



#ifndef __ASSEMBLY__

arch/mips/netlogic/xlp/nlm_hal.c

+16 −0
Original line number Diff line number Diff line
@@ -69,6 +69,14 @@ int nlm_irq_to_irt(int irq) 
		return PIC_IRT_UART_0_INDEX;

	case PIC_UART_1_IRQ:

		return PIC_IRT_UART_1_INDEX;

	case PIC_PCIE_LINK_0_IRQ:

	       return PIC_IRT_PCIE_LINK_0_INDEX;

	case PIC_PCIE_LINK_1_IRQ:

	       return PIC_IRT_PCIE_LINK_1_INDEX;

	case PIC_PCIE_LINK_2_IRQ:

	       return PIC_IRT_PCIE_LINK_2_INDEX;

	case PIC_PCIE_LINK_3_IRQ:

	       return PIC_IRT_PCIE_LINK_3_INDEX;

	default:

		return -1;

	}
@@ -81,6 +89,14 @@ int nlm_irt_to_irq(int irt) 
		return PIC_UART_0_IRQ;

	case PIC_IRT_UART_1_INDEX:

		return PIC_UART_1_IRQ;

	case PIC_IRT_PCIE_LINK_0_INDEX:

	       return PIC_PCIE_LINK_0_IRQ;

	case PIC_IRT_PCIE_LINK_1_INDEX:

	       return PIC_PCIE_LINK_1_IRQ;

	case PIC_IRT_PCIE_LINK_2_INDEX:

	       return PIC_PCIE_LINK_2_IRQ;

	case PIC_IRT_PCIE_LINK_3_INDEX:

	       return PIC_PCIE_LINK_3_IRQ;

	default:

		return -1;

	}

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