Commit 0dccdba5 authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

Merge tag 'gvt-fixes-2020-10-30' of https://github.com/intel/gvt-linux into drm-intel-fixes 



gvt-fixes-2020-10-30

- Fix HWSP reset handling during vGPU suspend/resume (Colin)
- Apply flush workaround on APL now for possible guest hang (Colin)
- Fix vGPU context pin/unpin also for host suspend regression with
  vGPU created (Colin)
- more BXT/APL mmio cmd access fixes (Colin)

Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201030052117.GC27141@zhen-hp.sh.intel.com
parents 3cea11cd 92010a97

drivers/gpu/drm/i915/gvt/handlers.c

+44 −3
Original line number Diff line number Diff line
@@ -1489,7 +1489,8 @@ static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, 
	const struct intel_engine_cs *engine =

		intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);



	if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {

	if (value != 0 &&

	    !intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {

		gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",

			      offset, value);

		return -EINVAL;
@@ -1650,6 +1651,34 @@ static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu, 
	return 0;

}



/**

 * FixMe:

 * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did:

 * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.)

 * Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing

 * these MI_BATCH_BUFFER.

 * Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT

 * PML4 PTE: PAT(0) PCD(1) PWT(1).

 * The performance is still expected to be low, will need further improvement.

 */

static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset,

			      void *p_data, unsigned int bytes)

{

	u64 pat =

		GEN8_PPAT(0, CHV_PPAT_SNOOP) |

		GEN8_PPAT(1, 0) |

		GEN8_PPAT(2, 0) |

		GEN8_PPAT(3, CHV_PPAT_SNOOP) |

		GEN8_PPAT(4, CHV_PPAT_SNOOP) |

		GEN8_PPAT(5, CHV_PPAT_SNOOP) |

		GEN8_PPAT(6, CHV_PPAT_SNOOP) |

		GEN8_PPAT(7, CHV_PPAT_SNOOP);



	vgpu_vreg(vgpu, offset) = lower_32_bits(pat);



	return 0;

}



static int guc_status_read(struct intel_vgpu *vgpu,

			   unsigned int offset, void *p_data,

			   unsigned int bytes)
@@ -2812,7 +2841,7 @@ static int init_bdw_mmio_info(struct intel_gvt *gvt) 


	MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);



	MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);

	MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);

	MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);



	MMIO_D(GAMTARBMODE, D_BDW_PLUS);
@@ -3139,7 +3168,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) 
		 NULL, NULL);



	MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);

	MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS);

	MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);



	return 0;

}
@@ -3313,9 +3342,21 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt) 
	MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);

	MMIO_D(GEN6_GFXPAUSE, D_BXT);

	MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);

	MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,

	       0, 0, D_BXT, NULL, NULL);

	MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,

	       0, 0, D_BXT, NULL, NULL);

	MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,

	       0, 0, D_BXT, NULL, NULL);

	MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,

	       0, 0, D_BXT, NULL, NULL);



	MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);



	MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);



	return 0;

}

drivers/gpu/drm/i915/gvt/scheduler.c

+8 −7
Original line number Diff line number Diff line
@@ -1277,7 +1277,7 @@ void intel_vgpu_clean_submission(struct intel_vgpu *vgpu) 


	i915_context_ppgtt_root_restore(s, i915_vm_to_ppgtt(s->shadow[0]->vm));

	for_each_engine(engine, vgpu->gvt->gt, id)

		intel_context_unpin(s->shadow[id]);

		intel_context_put(s->shadow[id]);



	kmem_cache_destroy(s->workloads);

}
@@ -1369,11 +1369,6 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu) 
			ce->ring = __intel_context_ring_size(ring_size);

		}



		ret = intel_context_pin(ce);

		intel_context_put(ce);

		if (ret)

			goto out_shadow_ctx;



		s->shadow[i] = ce;

	}
@@ -1405,7 +1400,6 @@ out_shadow_ctx: 
		if (IS_ERR(s->shadow[i]))

			break;



		intel_context_unpin(s->shadow[i]);

		intel_context_put(s->shadow[i]);

	}

	i915_vm_put(&ppgtt->vm);
@@ -1479,6 +1473,7 @@ void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload) 
{

	struct intel_vgpu_submission *s = &workload->vgpu->submission;



	intel_context_unpin(s->shadow[workload->engine->id]);

	release_shadow_batch_buffer(workload);

	release_shadow_wa_ctx(&workload->wa_ctx);
@@ -1724,6 +1719,12 @@ intel_vgpu_create_workload(struct intel_vgpu *vgpu, 
		return ERR_PTR(ret);

	}



	ret = intel_context_pin(s->shadow[engine->id]);

	if (ret) {

		intel_vgpu_destroy_workload(workload);

		return ERR_PTR(ret);

	}



	return workload;

}

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